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am1802 sprs710e ? november 2010 ? revised march 2014 am1802 arm ? microprocessor 1 am1802 arm microprocessor 1.1 features 1 ? 300-mhz arm926ej-s ? risc mpu ? two serial peripheral interfaces (spis) each with multiple chip selects ? arm926ej-s core ? one multimedia card (mmc)/secure digital (sd) ? 32-bit and 16-bit ( thumb ? ) instructions card interfaces with secure data i/o (sdio) ? single-cycle mac interfaces ? arm jazelle ? technology ? one master and slave inter-integrated circuit ( i 2 c ? embedded ice-rt ? for real-time debug bus ? ) ? arm9 ? memory architecture ? usb 2.0 otg port with integrated phy (usb0) ? 16kb of instruction cache ? usb 2.0 high- and full-speed client ? 16kb of data cache ? usb 2.0 high-, full-, and low-speed host ? 8kb of ram (vector table) ? end point 0 (control) ? 64kb of rom ? end points 1, 2, 3, 4 (control, bulk, interrupt or ? enhanced direct memory access controller 3 isoc) rx and tx (edma3): ? one multichannel audio serial port (mcasp): ? 2 channel controllers ? transmit and receive clocks ? 3 transfer controllers ? two clock zones and 16 serial data pins ? 64 independent dma channels ? supports tdm, i2s, and similar formats ? 16 quick dma channels ? dit-capable ? programmable transfer burst size ? fifo buffers for transmit and receive ? 128kb of on-chip memory ? 10/100 mbps ethernet mac (emac): ? 1.8-v or 3.3-v lvcmos i/os (except for usb and ? ieee 802.3 compliant ddr2 interfaces) ? mii media-independent interface ? two external memory interfaces: ? rmii reduced media-independent interface ? emifa ? management data i/o (mdio) module ? nor (8- or 16-bit-wide data) ? real-time clock (rtc) with 32-khz oscillator and ? nand (8- or 16-bit-wide data) separate power rail ? 16-bit sdram with 128-mb address space ? three 64-bit general-purpose timers (each ? ddr2/mobile ddr memory controller with one configurable as two 32-bit timers) of the following: ? one 64-bit general-purpose or watchdog timer ? 16-bit ddr2 sdram with 256-mb address (configurable as two 32-bit general-purpose space timers) ? 16-bit mddr sdram with 256-mb address ? packages: space ? 361-ball pb-free plastic ball grid array (pbga) ? three configurable 16550-type uart modules: [zce suffix], 0.65-mm ball pitch ? with modem control signals ? 361-ball pbga [zwt suffix], 0.80-mm ball pitch ? 16-byte fifo ? industrial temperature ? 16x or 13x oversampling option 1.2 applications ? medical, healthcare, and fitness ? epos ? building automation 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder sample &buy technical documents tools & software support &community
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 1.3 description the am1802 arm microprocessor is a low-power applications processor based on arm926ej-s. the device enables original-equipment manufacturers (oems) and original-design manufacturers (odms) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. the arm926ej-s is a 32-bit risc processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. the core uses pipelining so that all parts of the processor and memory system can operate continuously. the arm core has a coprocessor 15 (cp15), protection module, and data and program memory management units (mmus) with table look-aside buffers. the arm core processor has separate 16-kb instruction and 16-kb data caches. both are four-way associative with virtual index virtual tag (vivt). the arm core also has 8kb of ram (vector table) and 64kb of rom. the peripheral set includes: a 10/100 mbps ethernet media access controller (emac) with a management data input/output (mdio) module; one usb2.0 otg interface; one inter-integrated circuit (i 2 c bus) interface; one multichannel audio serial port (mcasp) with 16 serializers and fifo buffers; two serial peripheral interfaces (spis) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (hpi); up to 9 banks of general-purpose input/output (gpio) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three uart interfaces (each with rts and cts); two external memory interfaces: an asynchronous and sdram external memory interface (emifa) for slower memories or peripherals; and a higher speed ddr2/mobile ddr controller. the emac provides an efficient interface between the device and a network. the emac supports both 10base-t and 100base-tx, or 10 mbps and 100 mbps in either half- or full-duplex mode. additionally, an mdio interface is available for phy configuration. the emac supports both mii and rmii interfaces. the rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. for details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. the device has a complete set of development tools for the arm processor. these tools include c compilers, and scheduling, and a windows ? debugger interface for visibility into source code execution. device information part number package body size am1802zwt nfbga (361) 16,00 mm x 16,00 mm am1802zce nfbga (361) 13,00 mm x 13,00 mm 2 am1802 arm microprocessor copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 1.4 functional block diagram figure 1-1 shows the functional block diagram of the device. figure 1-1. functional block diagram copyright ? 2010 ? 2014, texas instruments incorporated am1802 arm microprocessor 3 submit documentation feedback product folder links: am1802 switched central resource (scr) 16kb i-cache 16kb d-cache 4kb etb arm926ej-s cpu with mmu arm subsystem jtag interface system control input clock(s) 64kb rom 8kb ram (vector table) power/sleep controller pin multiplexing pll/clock generator w/osc general- purpose timer (x3) serial interfaces audio ports mcasp w/fifo dma peripherals internal memory 128kb ram external memory interfaces connectivity edma3 (x2) emifa(8b/16b) nand/flash 16b sdram ddr2/mddr controller rtc/ 32-khz osc i c 2 (x1) spi (x2) uart (x3) emac 10/100 (mii/rmii) mdio usb2.0 otg ctlr phy mmc/sd (8b) (x1) memory protection
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table of contents 1 am1802 arm microprocessor ......................... 1 6.4 reset ................................................ 50 1.1 features .............................................. 1 6.5 crystal oscillator or external clock input ........... 54 1.2 applications ........................................... 1 6.6 clock plls .......................................... 55 1.3 description ............................................ 2 6.7 interrupts ............................................ 60 1.4 functional block diagram ............................ 3 6.8 power and sleep controller (psc) .................. 65 2 revision history ......................................... 5 6.9 edma ............................................... 70 3 device overview ......................................... 6 6.10 external memory interface a (emifa) .............. 76 3.1 device characteristics ................................ 6 6.11 ddr2/mddr controller ............................. 86 3.2 device compatibility .................................. 6 6.12 memory protection units ............................ 99 3.3 arm subsystem ...................................... 6 6.13 mmc / sd / sdio (mmcsd0) ..................... 102 3.4 memory map summary .............................. 9 6.14 multichannel audio serial port (mcasp) .......... 105 3.5 pin assignments .................................... 11 6.15 serial peripheral interface ports (spi0, spi1) ..... 114 3.6 pin multiplexing control ............................. 14 6.16 inter-integrated circuit serial ports (i2c) .......... 135 6.17 universal asynchronous receiver/transmitter 3.7 terminal functions .................................. 15 (uart) ............................................. 139 3.8 unused pin configurations .......................... 37 6.18 universal serial bus otg controller (usb0) 4 device configuration .................................. 39 [usb2.0 otg] ..................................... 141 4.1 boot modes ......................................... 39 6.19 ethernet media access controller (emac) ........ 148 4.2 syscfg module .................................... 39 6.20 management data input/output (mdio) ........... 155 4.3 pullup/pulldown resistors .......................... 42 6.21 timers .............................................. 157 5 specifications ........................................... 43 6.22 real time clock (rtc) ............................ 159 5.1 absolute maximum ratings over operating 6.23 general-purpose input/output (gpio) ............. 162 junction temperature range (unless otherwise noted) ................................. 43 6.24 emulation logic .................................... 166 5.2 handling ratings .................................... 43 7 device and documentation support .............. 174 5.3 recommended operating conditions ............... 44 7.1 device support ..................................... 174 5.4 notes on recommended power-on hours (poh) . 46 7.2 documentation support ............................ 175 5.5 electrical characteristics over recommended 7.3 community resources ............................. 175 ranges of supply voltage and operating junction 7.4 trademarks ........................................ 175 temperature (unless otherwise noted) ............ 47 7.5 electrostatic discharge caution ................... 176 6 peripheral information and electrical 7.6 glossary ............................................ 176 specifications ........................................... 48 8 mechanical packaging and orderable 6.1 parameter information .............................. 48 information ............................................. 176 6.2 recommended clock and control signal transition 8.1 thermal data for zce package ................... 176 behavior ............................................. 49 8.2 thermal data for zwt package ................... 177 6.3 power supplies ...................................... 49 8.3 packaging information ............................. 177 4 table of contents copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 2 revision history note: page numbers for previous revisions may differ from page numbers in the current version. this data manual revision history highlights the changes made to the sprs710d device-specific data manual to make it an sprs710e revision. revision history see additions/modifications/deletions ? moved trademarks information from first page to within section 7 , device and documentation support. global ? moved esds warning to within section 7 , device and documentation support. ? updated features, applications, and description for consistency and translation. section 1.3 added new device information table. description table 3-3 thru table 3-18 : section 3.7 ? updated/changed footnote beginning with "ipd = internal pulldown resistor..."; added terminal functions sentence "for more detailed information on pullup/pulldown..." table 3-15 , universal serial bus (usb) terminal functions section 3.7.13 universal serial bus modules ? updated/changed the capacitor value in usb0_vdda12 pin description from "1 f" to (usb0) " 0.22- f " table 3-21 , unused usb0 signal configurations: section 3.8 ? updated/changed usb0_vdda12 row text from "no connect" to " ...to an external 0.22- f unused pin configurations filter capacitor " updated/changed title from "device operating conditions" to "specifications" section 5.2 , handling ratings: section 5 specifications ? split handling, ratings, and certifications from the abs max table and placed in new handling ratings table. section 5.4 table 5-1 , recommended power-on hours: notes on recommended ? updated/changed all applicable silicon revisions from "b" to " b/e " power-on hours figure 6-12 , asynchronous memory read timing for emifa: section 6.10.5 ? added vertical lines to show difference between setup, strobe, and hold emifa electrical/timing figure 6-13 , asynchronous memory write timing for emifa: ? added vertical lines to show difference between setup, strobe, and hold section 7.1.2 figure 7-1 , device nomenclature: device and development- ? added "e = silicon revision 2.3" under silicon revision support tool nomenclature section 7.6 added new section. glossary copyright ? 2010 ? 2014, texas instruments incorporated revision history 5 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3 device overview 3.1 device characteristics table 3-1 provides an overview of the device. the table shows significant features of the device, including the capacity of on-chip ram, peripherals, and the package type with pin count. table 3-1. characteristics of the device hardware features am1802 ddr2, 16-bit bus width, up to 156 mhz ddr2/mddr controller mobile ddr, 16-bit bus width, up to 150 mhz asynchronous (8/16-bit bus width) ram, flash, emifa 16-bit sdram, nor, nand flash card interface mmc and sd cards supported 64 independent channels, 16 qdma channels, edma3 peripherals 2 channel controllers, 3 transfer controllers 4 64-bit general purpose (each configurable as 2 separate not all peripherals pins timers 32-bit timers, one configurable as watch dog) are available at the same time (for more uart 3 (each with rts and cts flow control) detail, see the device spi 2 (each with multiple chip selects) configurations section). i 2 c 1 (master/slave) multichannel audio serial port [mcasp] 1 (each with transmit/receive, fifo buffer, 16 serializers) 10/100 ethernet mac with management data i/o 1 (mii or rmii interface) usb 2.0 (usb0) high-speed otg controller with on-chip otg phy general-purpose input/output port 9 banks of 16-bit size (bytes) 168kb ram arm 16kb i-cache 16kb d-cache on-chip memory organization 8kb ram (vector table) 64kb rom additional memory 128kb ram jtag bsdl_id devidr0 register 0x0b7d_102f cpu frequency mhz arm926 300 mhz (1.2v) core (v) 1.2 v nominal for 300 mhz voltage i/o (v) 1.8 v or 3.3 v 13 mm x 13 mm, 361-ball 0.65 mm pitch, pbga (zce) packages 16 mm x 16 mm, 361-ball 0.80 mm pitch, pbga (zwt) product preview (pp), product status (1) advance information (ai), pd or production data (pd) (1) production data information is current as of publication date. products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 3.2 device compatibility the arm926ej-s risc cpu is compatible with other arm9 cpus from arm holdings plc. 3.3 arm subsystem the arm subsystem includes the following features: ? arm926ej-s risc processor ? armv5tej (32/16-bit) instruction set ? little endian ? system control co-processor 15 (cp15) 6 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 ? mmu ? 16kb instruction cache ? 16kb data cache ? write buffer ? embedded trace module and embedded trace buffer (etm/etb) ? arm interrupt controller 3.3.1 arm926ej-s risc cpu the arm subsystem integrates the arm926ej-s processor. the arm926ej-s processor is a member of arm9 family of general-purpose microprocessors. this processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. the arm926ej-s processor supports the 32-bit arm and 16 bit thumb instruction sets, enabling the user to trade off between high performance and high code density. specifically, the arm926ej-s processor supports the armv5tej instruction set, which includes features for efficient execution of java byte codes, providing java performance similar to just in time (jit) java interpreter, but without associated code overhead. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debug. the arm926ej-s processor has a harvard architecture and provides a complete high performance subsystem, including: ? arm926ej -s integer core ? cp15 system control coprocessor ? memory management unit (mmu) ? separate instruction and data caches ? write buffer ? separate instruction and data (internal ram) interfaces ? separate instruction and data ahb bus interfaces ? embedded trace module and embedded trace buffer (etm/etb) for more complete details on the arm9, refer to the arm926ej-s technical reference manual, available at http://www.arm.com 3.3.2 cp15 the arm926ej-s system control coprocessor (cp15) is used to configure and control instruction and data caches, memory management unit (mmu), and other arm subsystem functions. the cp15 registers are programmed using the mrc and mcr arm instructions, when the arm in a privileged mode such as supervisor or system mode. 3.3.3 mmu a single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. the mmu uses a single unified translation lookaside buffer (tlb) to cache the information held in the page tables. the mmu features are: ? standard arm architecture v4 and v5 mmu mapping sizes, domains and access protection scheme. ? mapping sizes are: ? 1mb (sections) ? 64kb (large pages) ? 4kb (small pages) ? 1kb (tiny pages) ? access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) copyright ? 2010 ? 2014, texas instruments incorporated device overview 7 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com ? hardware page table walks ? invalidate entire tlb, using cp15 register 8 ? invalidate tlb entry, selected by mva, using cp15 register 8 ? lockdown of tlb entries, using cp15 register 10 3.3.4 caches and write buffer the size of the instruction cache is 16kb, data cache is 16kb. additionally, the caches have the following features: ? virtual index, virtual tag, and addressed using the modified virtual address (mva) ? four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the dcache ? dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the c and b bits in the mmu translation tables ? critical-word first cache refilling ? cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption ? dcache stores the physical address tag (pa tag) corresponding to each dcache entry in the tag ram for use during the cache line write-backs, in addition to the virtual address tag stored in the tag ram. this means that the mmu is not involved in dcache write-back operations, removing the possibility of tlb misses related to the write-back address. ? cache maintenance operations provide efficient invalidation of, the entire dcache or icache, regions of the dcache or icache, and regions of virtual memory. the write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. a separate buffer is incorporated in the dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. the main write buffer has 16-word data buffer and a four-address buffer. the dcache write-back has eight data word entries and a single address entry. 3.3.5 advanced high-performance bus (ahb) the arm subsystem uses the ahb port of the arm926ej-s to connect the arm to the config bus and the external memories. arbiters are employed to arbitrate access to the separate d-ahb and i-ahb by the config bus and the external memories bus. 3.3.6 embedded trace macrocell (etm) and embedded trace buffer (etb) to support real-time trace, the arm926ej-s processor provides an interface to enable connection of an embedded trace macrocell (etm). the arm926es-j subsystem in the device also includes the embedded trace buffer (etb). the etm consists of two parts: ? trace port provides real-time trace capability for the arm9. ? triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. the device trace port is not pinned out and is instead only connected to the embedded trace buffer. the etb has a 4kb buffer memory. etb enabled debug tools are required to read/interpret the captured trace data. 3.3.7 arm memory mapping by default the arm has access to most on and off chip memory areas, including emifa, ddr2, and the additional 128k byte on chip sram. likewise almost all of the on chip peripherals are accessible to the arm by default. see table 3-2 for a detailed top level device memory map that includes the arm memory space. 8 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.4 memory map summary note: read/write accesses to illegal or reserved addresses in the memory map may cause undefined behavior. table 3-2. am1802 top level memory map start address end address size arm mem map edma mem map master peripheral mem map 0x0000 0000 0x01bb ffff 0x01bc 0000 0x01bc 0fff 4k arm etb memory 0x01bc 1000 0x01bc 17ff 2k arm etb reg 0x01bc 1800 0x01bc 18ff 256 arm ice crusher 0x01bc 1900 0x01bf ffff 0x01c0 0000 0x01c0 7fff 32k edma3 cc 0x01c0 8000 0x01c0 83ff 1k edma3 tc0 0x01c0 8400 0x01c0 87ff 1k edma3 tc1 0x01c0 8800 0x01c0 ffff 0x01c1 0000 0x01c1 0fff 4k psc 0 0x01c1 1000 0x01c1 1fff 4k pll controller 0 0x01c1 2000 0x01c1 3fff 0x01c1 4000 0x01c1 4fff 4k syscfg0 0x01c1 5000 0x01c1 ffff 0x01c2 0000 0x01c2 0fff 4k timer0 0x01c2 1000 0x01c2 1fff 4k timer1 0x01c2 2000 0x01c2 2fff 4k i2c 0 0x01c2 3000 0x01c2 3fff 4k rtc 0x01c2 4000 0x01c3 ffff 0x01c4 0000 0x01c4 0fff 4k mmc/sd 0 0x01c4 1000 0x01c4 1fff 4k spi 0 0x01c4 2000 0x01c4 2fff 4k uart 0 0x01c4 3000 0x01cf ffff 0x01d0 0000 0x01d0 0fff 4k mcasp 0 control 0x01d0 1000 0x01d0 1fff 4k mcasp 0 afifo ctrl 0x01d0 2000 0x01d0 2fff 4k mcasp 0 data 0x01d0 3000 0x01d0 bfff 0x01d0 c000 0x01d0 cfff 4k uart 1 0x01d0 d000 0x01d0 dfff 4k uart 2 0x01d0 e000 0x01df ffff 0x01e0 0000 0x01e0 ffff 64k usb0 0x01e1 0000 0x01e1 3fff 0x01e1 4000 0x01e1 4fff 4k memory protection unit 1 (mpu 1) 0x01e1 5000 0x01e1 5fff 4k memory protection unit 2 (mpu 2) 0x01e1 6000 0x01e1 9fff 0x01e1 a000 0x01e1 afff 4k pll controller 1 0x01e1 b000 0x01e1 ffff 0x01e2 0000 0x01e2 1fff 8k emac control module ram 0x01e2 2000 0x01e2 2fff 4k emac control module registers 0x01e2 3000 0x01e2 3fff 4k emac control registers 0x01e2 4000 0x01e2 4fff 4k emac mdio port 0x01e2 5000 0x01e2 5fff 0x01e2 6000 0x01e2 6fff 4k gpio copyright ? 2010 ? 2014, texas instruments incorporated device overview 9 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 3-2. am1802 top level memory map (continued) start address end address size arm mem map edma mem map master peripheral mem map 0x01e2 7000 0x01e2 7fff 4k psc 1 0x01e2 8000 0x01e2 bfff 0x01e2 c000 0x01e2 cfff 4k syscfg1 0x01e2 d000 0x01e2 ffff 0x01e3 0000 0x01e3 7fff 32k edma3 cc1 0x01e3 8000 0x01e3 83ff 1k edma3 tc2 0x01e3 8400 0x01f0 bfff 0x01f0 c000 0x01f0 cfff 4k timer2 0x01f0 d000 0x01f0 dfff 4k timer3 0x01f0 e000 0x01f0 efff 4k spi1 0x01f0 f000 0x3fff ffff 0x4000 0000 0x5fff ffff 512m emifa sdram data (cs0) 0x6000 0000 0x61ff ffff 32m emifa async data (cs2) 0x6200 0000 0x63ff ffff 32m emifa async data (cs3) 0x6400 0000 0x65ff ffff 32m emifa async data (cs4) 0x6600 0000 0x67ff ffff 32m emifa async data (cs5) 0x6800 0000 0x6800 7fff 32k emifa control regs 0x6800 8000 0x7fff ffff 0x8000 0000 0x8001 ffff 128k on-chip ram 0x8002 0000 0xafff ffff 0xb000 0000 0xb000 7fff 32k ddr2/mddr control regs 0xb000 8000 0xbfff ffff 0xc000 0000 0xcfff ffff 256m ddr2/mddr data 0xd000 0000 0xe000 0000 0xfffd 0000 0xfffd ffff 64k arm local rom 0xfffe 0000 0xfffe dfff 0xfffe e000 0xfffe ffff 8k arm interrupt controller 0xffff 0000 0xffff 1fff 8k arm local ram 0xffff 2000 0xffff ffff 10 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.5 pin assignments extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 3.5.1 pin map (bottom view) the following graphics show the bottom view of the zce and zwt package pin assignments in four quadrants (a, b, c, and d). the pin assignments for both packages are identical. figure 3-1. pin map (quad a) copyright ? 2010 ? 2014, texas instruments incorporated device overview 11 submit documentation feedback product folder links: am1802 w v u t r p n m l k 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 dvdd3318_c gp6[1] vss nc_l1 gp6[3] nc_l2 nc_m2 nc_n1 nc_n3 nc_n2 nc_n4 nc_p1 nc_p3 nc_p2 dvdd3318_c ddr_a[11] gp7[7]/ boot[7] dv dd3318_c dv dd18 ddr_dvdd18 ddr_dvdd18 ddr_d[15] ddr_ras ddr_clkp ddr_clkn ddr_a[2] ddr_a[10] v ss gp6[0] ddr_a[13] ddr_cas ddr_a[5] ddr_cke ddr_ba[0] v ss cv dd rv dd ddr_a[9] ddr_a[1] ddr_we ddr_d[10] ddr_a[7] ddr_a[0] ddr_d[12] ddr_a[12] ddr_a[3] ddr_cs ddr_a[6] ddr_dqm[1] vss cv dd vss ddr_dvdd18 gp7[4]/ boot[4] ddr_vref ddr_ba[1] ddr_a[8] ddr_a[4] ddr_ba[2] vss wv u t r p n m l k ddr_d[13] v ss v ss v ss v ss dv dd18 v ss v ss v ss v ss nc_m3 v ss v ss v ss v ss cv dd cv dd v ss ddr_dvdd18 ddr_dvdd18 ddr_dvdd18 ddr_dvdd18 dvdd3318_c gp7[5]/ boot[5] gp7[6]/ boot[6] ddr_dvdd18 ddr_dvdd18 ddr_dvdd18 gp7[1]/ boot[1] gp7[2]/ boot[2] gp7[3]/ boot[3] gp7[14] gp7[15] gp7[0]/ boot[0] gp7[11] gp7[12] gp7[13] gp7[8] gp7[9] gp7[10] a b c d
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 3-2. pin map (quad b) 12 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 w v u t r p n m l k 19 18 17 16 15 14 13 12 11 19 18 17 16 15 14 13 12 11 nc_p15 dvdd3318_c cv dd usb_cvdd dvdd3318_c ddr_dqgate0 dvdd18 ddr_dqgate1 ddr_d[9] ddr_d[8] ddr_d[11] dvdd18 rtc_cvdd reset usb0_dm usb0_dp nc_r18 usb0_vdda33 usb0_vbus nc_p18 rmii_crs_dv rmii_mhz_50_clk rmii_rxer rmii_rxd[1] gp6[10] nc_p19 pll0_vdda gp6[12] usb0_vdda18 rmii_txen ddr_d[1] rmii_txd[1] oscvss ddr_d[2] rmii_txd[0] rmii_rxd[0] nc_v19 emu1 gp6[5] usb0_vdda12 tdi nc_n16 gp6[8] nc_t16 resetout/ gp6[15] rsv2 rtck/ gp8[0] oscout ddr_d[0] gp6[9] nc_u19 trst oscin gp6[6] nc_v18 gp6[7] nc_r19 v ss dvdd3318_b pll0_vssa tms gp6[13] nc pll1_vssa pll1_vdda nc_p14 usb0_id nc_r15 clkout/ gp6[14] usb0_drvvbus ddr_dqs[0] gp6[11] wv u t r p n m l k ddr_dqm[0] ddr_d[3] ddr_d[4] ddr_d[6] ddr_zp ddr_d[5] ddr_d[7] ddr_d[14] ddr_dqs[1] v ss v ss v ss v ss v ss cv dd dvdd3318_c dvdd3318_c dvdd3318_c aa b c d
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 3-3. pin map (quad c) copyright ? 2010 ? 2014, texas instruments incorporated device overview 13 submit documentation feedback product folder links: am1802 h g f e d c b a 19 18 17 16 15 14 13 12 11 19 18 17 16 15 14 13 12 11 cv dd ema_a[8]/ gp5[8] ema_a[14]/ mmcsd0_dat[7]/ gp5[14] ema_a[15]/ mmcsd0_dat[6]/ gp5[15] ema_a[10]/ gp5[10] ema_a[9]/ gp5[9] ema_a[13]/ gp5[13] ema_a[12]/ gp5[12] ema_a[16]/ mmcsd0_dat[5]/ gp4[0] ema_a[18]/ mmcsd0_dat[3]/ gp4[2] dv dd3318_b dv dd18 ema_a[6]/ gp5[6] ema_a[5]/ gp5[5] ema_a[2]/ gp5[2] ema_a7/ gp5[7] ema_a[4]/ gp5[4] spi0_simo/ gp8[5]/ mii_crs spi0_scs[5]/ uart0_rxd/ gp8[4]/ mii_rxd[3] spi1_scs[1]/ gp2[15]/ tm64p2_in12 spi0_scs[4]/ uart0_txd/ gp8[3]/ mii_rxd[2] spi0_clk/ gp1[8]/ mii_rxclk spi1_scs[3]/ uart1_rxd/ gp1[1] spi1_scs[0]/ gp2[14]/ tm64p3_in12 ema_oe/ gp3[10] spi1_scs[4]/ uart2_txd/ gp1[2] ema_a[3]/ gp5[3] dv dd18 rtc_vss ema_wait[0]/ gp3[8] ema_ras/ gp2[5] spi0_scs[3] uart0_cts / / gp8[2]/ mii_rxd[1] spi0_scs[0]/ tm64p1_out12/ gp1[6]/ mdio/ tm64p1_in12 spi0_somi/ gp8[6]/ mii_rxer spi0_scs[2] uart0_rts / / gp8[1]/ mii_rxd[0] spi1_scs[7]/ i2c0_scl/ tm64p2_out12/ gp1[5] spi1_simo/ gp2[10] spi1_clk/ gp2[13] ema_cs[3]/ gp3[14] v ss v ss spi1_ena/ gp2[12] rtc_xo ema_cs[2]/ gp3[15] ema_wait[1]/ gp2[1] ema_a[20]/ mmcsd0_dat[1]/ gp4[4] ema_ba[1]/ gp2[9] spi0_ena/ mii_rxdv ema_cs[5]/ gp3[12] spi1_scs[5]/ uart2_rxd/ gp1[3] ema_a[0]/ gp5[0] ema_ba[0]/ gp2[8] ema_a[1]/ gp5[1] dv dd3318_b spi0_scs[1]/ tm64p0_out12/ gp1[7]/ mdclk/ tm64p0_in12 dv dd3318_a spi1_scs[6]/ i2c0_sda/ tm64p3_out12/ gp1[4] ema_cs[0]/ gp2[0] cv dd spi1_somi/ gp2[11] h g f e dc b a j tdo tck emu0 rtc_xi rsvdn j spi1_scs[2]/ uart1_txd/ gp1[0] ema_a[11]/ gp5[11] ema_a[17]/ mmcsd0_dat[4]/ gp4[1] dv dd3318_b dv dd3318_b dv dd18 cv dd dv dd3318_a dv dd3318_a rv dd cv dd cv dd v ss cv dd dv dd18 dv dd3318_b c a b d
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 3-4. pin map (quad d) 3.6 pin multiplexing control device level pin multiplexing is controlled by registers pinmux0 - pinmux19 in the syscfg module. for the device family, pin multiplexing can be controlled on a pin-by-pin basis. each pin that is multiplexed with several different functions has a corresponding 4-bit field in one of the pinmux registers. pin multiplexing selects which of several peripheral pin functions controls the pin's io buffer output data and output enable values only. the default pin multiplexing control for almost every pin is to select 'none' of the peripheral functions in which case the pin's io buffer is held tri-stated. note that the input from each pin is always routed to all of the peripherals that share the pin; the pinmux registers have no effect on input from a pin. 14 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 j h g f e d c b a 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 ema_d[15]/ gp3[7] axr15/ gp0[7] aclkr/ gp0[15] aclkx/ gp0[14] ahclkx/ usb_refclkin/ / gp0[10] uart1_cts afsx/ gp0[12] afsr/ gp0[13] axr9/ gp0[1] axr4/ gp1[12]/ mii_col axr5/ gp1[13]/ mii_txclk axr7/ gp1[15] axr10/ gp0[2] axr1/ gp1[9]/ mii_txd[1] axr3/ gp1[11]/ mii_txd[3] axr2/ gp1[10]/ mii_txd[2] gp8[10] rtc_alarm/ / gp0[8]/ uart2_cts deepsleep axr0/ gp8[7]/ mii_txd[0] gp8[14] gp8[8] vss gp8[12] axr8/ gp0[0] axr12/ gp0[4] ema_d[4]/ gp4[12] axr14/ gp0[6] ema_wen_dqm[1]/ gp2[2] ema_d[0]/ gp4[8] ema_a[19]/ mmcsd0_dat[2]/ gp4[3] ema_d[9]/ gp3[1] ema_a_r / gp3[9] w mmcsd0_clk/ gp4[7] ema_d[8]/ gp3[0] ema_d[13]/ gp3[5] gp6[4] gp6[2] amute/ gp0[9] uart2_rts/ dv dd3318_a dv dd3318_a ema_we/ gp3[11] ema_d[10]/ gp3[2] ema_d[3]/ gp4[11] ema_sdcke/ gp2[6] ema_d[14]/ gp3[6] ema_d[7]/ gp4[15] ema_d[1]/ gp4[9] ema_a[22]/ mmcsd0_cmd/ gp4[6] ema_d[2]/ gp4[10] ema_a[21]/ mmcsd0_dat[0]/ gp4[5] gp8[13] ahclkr/ / gp0[11] uart1_rts ema_d[12]/ gp3[4] ema_wen_dqm[0]/ gp2[3] ema_clk/ gp2[7] axr6/ gp1[14]/ mii_txen axr11/ gp0[3] ema_d[6]/ gp4[14] ema_d[11]/ gp3[3] rv dd ema_d[5]/ gp4[13] gp8[11] gp8[9] gp8[15] axr13/ gp0[5] jh g f e d c b a ema_cs[4]/ gp3[13] ema_cas/ gp2[4] dv dd3318_b dv dd3318_b dv dd3318_b dv dd3318_b dv dd18 cv dd cv dd dv dd3318_b dv dd18 vss dv dd3318_a v ss v ss cv dd cv dd v ss v ss cv dd nc_j1 nc_j2 dv dd3318_c cv dd v ss v ss a b c d
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7 terminal functions table 3-3 to table 3-20 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (i, o, io, oz, or pwr), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an io in gpio mode, and a functional pin description. 3.7.1 device reset and jtag table 3-3. reset and jtag terminal functions signal power type (1) pull (2) description group (3) name no. reset reset k14 i ipu b device reset input resetout / gp6[15] t17 o (4) cp[21] c reset output jtag tms l16 i ipu b jtag test mode select tdi m16 i ipu b jtag test data input tdo j18 o ipu b jtag test data output tck j15 i ipu b jtag test clock trst l17 i ipd b jtag test reset emu0 j16 i/o ipu b emulation pin emu1 k16 i/o ipu b emulation pin jtag test clock return clock output rtck / gp8[0] (5) k17 i/o ipd b general-purpose input/output (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor, ipu = internal pullup resistor. cp[n] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. (4) open drain mode for resetout function. (5) gp8[0] is initially configured as a reserved function after reset and will not be in a predictable state. this signal will only be stable after the gpio configuration for this pin has been completed. users should carefully consider the system implications of this pin being in an unknown state after reset. copyright ? 2010 ? 2014, texas instruments incorporated device overview 15 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.2 high-frequency oscillator and pll table 3-4. high-frequency oscillator and pll terminal functions signal power type (1) pull (2) description group (3) name no. clkout / gp6[14] t18 o cp[22] c pll observation clock 1.2-v oscillator oscin l19 i ? ? oscillator input oscout k19 o ? ? oscillator output oscvss l18 gnd ? ? oscillator ground 1.2-v pll0 pll0_vdda l15 pwr ? ? pll analog v dd (1.2-v filtered supply) pll0_vssa m17 gnd ? ? pll analog v ss (for filter) 1.2-v pll1 pll1_vdda n15 pwr ? ? pll analog v dd (1.2-v filtered supply) pll1_vssa m15 gnd ? ? pll analog v ss (for filter) (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 16 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7.3 real-time clock and 32-khz oscillator table 3-5. real-time clock (rtc) and 1.2-v, 32-khz oscillator terminal functions signal power type (1) pull (2) description group (3) name no. rtc_xi j19 i ? ? rtc 32-khz oscillator input rtc_xo h19 o ? ? rtc 32-khz oscillator output rtc_alarm / uart2_cts / gp0[8] / deepsleep f4 o cp[0] a rtc alarm rtc module core power rtc_cvdd l14 pwr ? ? (isolated from chip cv dd ) rtc_v ss h18 gnd ? ? oscillator ground (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 3.7.4 deepsleep power control table 3-6. deepsleep power control terminal functions signal power type (1) pull (2) description group (3) name no. rtc_alarm / uart2_cts / gp0[8] / deepsleep f4 i cp[0] a deepsleep power control output (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. copyright ? 2010 ? 2014, texas instruments incorporated device overview 17 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.5 external memory interface a (emifa) table 3-7. external memory interface a (emifa) terminal functions signal power type (1) pull (2) description group (3) name no. ema_d[15] / gp3[7] e6 i/o cp[17] b ema_d[14] / gp3[6] c7 i/o cp[17] b ema_d[13] / gp3[5] b6 i/o cp[17] b ema_d[12] / gp3[4] a6 i/o cp[17] b ema_d[11] / gp3[3] d6 i/o cp[17] b ema_d[10] / gp3[2] a7 i/o cp[17] b ema_d[9] / gp3[1] d9 i/o cp[17] b ema_d[8] / gp3[0] e10 i/o cp[17] b emifa data bus ema_d[7] / gp4[15] d7 i/o cp[17] b ema_d[6] / gp4[14] c6 i/o cp[17] b ema_d[5] / gp4[13] e7 i/o cp[17] b ema_d[4] / gp4[12] b5 i/o cp[17] b ema_d[3] / gp4[11] e8 i/o cp[17] b ema_d[2] / gp4[10] b8 i/o cp[17] b ema_d[1] / gp4[9] a8 i/o cp[17] b ema_d[0] / gp4[8] c9 i/o cp[17] b (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 18 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 3-7. external memory interface a (emifa) terminal functions (continued) signal power type (1) pull (2) description group (3) name no. ema_a[22] / mmcsd0_cmd / gp4[6] a10 o cp[18] b ema_a[21] / mmcsd0_dat[0] / gp4[5] b10 o cp[18] b ema_a[20] / mmcsd0_dat[1] / gp4[4] a11 o cp[18] b ema_a[19] / mmcsd0_dat[2] /gp4[3] c10 o cp[18] b ema_a[18] / mmcsd0_dat[3] / gp4[2] e11 o cp[18] b ema_a[17] / mmcsd0_dat[4] /gp4[1] b11 o cp[18] b ema_a[16] / mmcsd0_dat[5] / gp4[0] e12 o cp[18] b ema_a[15] / mmcsd0_dat[6] / gp5[15] c11 o cp[19] b ema_a[14] / mmcsd0_dat[7] / gp5[14] a12 o cp[19] b ema_a[13] / gp5[13] d11 o cp[19] b ema_a[12] / gp5[12] d13 o cp[19] b ema_a[11] / gp5[11] b12 o cp[19] b emifa address bus ema_a[10] / gp5[10] c12 o cp[19] b ema_a[9] / gp5[9] d12 o cp[19] b ema_a[8] / gp5[8] a13 o cp[19] b ema_a[7] / gp5[7] b13 o cp[20] b ema_a[6] / gp5[6] e13 o cp[20] b ema_a[5] / gp5[5] c13 o cp[20] b ema_a[4] / gp5[4] a14 o cp[20] b ema_a[3] / gp5[3] d14 o cp[20] b ema_a[2] / gp5[2] b14 o cp[20] b ema_a[1] / gp5[1] d15 o cp[20] b ema_a[0] / gp5[0] c14 o cp[20] b ema_ba[0] / gp2[8] c15 o cp[16] b emifa bank address ema_ba[1] / gp2[9] a15 o cp[16] b ema_clk / gp2[7] b7 o cp[16] b emifa clock ema_sdcke / gp2[6] d8 o cp[16] b emifa sdram clock enable ema_ras / gp2[5] a16 o cp[16] b emifa sdram row address strobe ema_cas / gp2[4] a9 o cp[16] b emifa sdram column address strobe ema_cs[0] / gp2[0] a18 o cp[16] b emifa sdram chip select ema_cs[2] / gp3[15] b17 o cp[16] b ema_cs[3] / gp3[14] a17 o cp[16] b emifa async chip select ema_cs[4] / gp3[13] f9 o cp[16] b ema_cs[5] / gp3[12] b16 o cp[16] b ema_a_r w / gp3[9] d10 o cp[16] b emifa async read/write control ema_we / gp3[11] b9 o cp[16] b emifa sdram write enable emifa write enable/data mask for ema_wen_dqm[1] / gp2[2] a5 o cp[16] b ema_d[15:8] ema_wen_dqm[0] / gp2[3] c8 o cp[16] b emifa write enable/data mask for ema_d[7:0] ema_oe / gp3[10] b15 o cp[16] b emifa output enable ema_wait[0] / gp3[8] b18 i cp[16] b emifa wait input/interrupt ema_wait[1] / gp2[1] b19 i cp[16] b copyright ? 2010 ? 2014, texas instruments incorporated device overview 19 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.6 ddr2/mddr memory controller table 3-8. ddr2/mddr terminal functions signal type (1) pull (2) description name no. ddr_d[15] w10 i/o ipd ddr_d[14] u11 i/o ipd ddr_d[13] v10 i/o ipd ddr_d[12] u10 i/o ipd ddr_d[11] t12 i/o ipd ddr_d[10] t10 i/o ipd ddr_d[9] t11 i/o ipd ddr_d[8] t13 i/o ipd ddr2 sdram data bus ddr_d[7] w11 i/o ipd ddr_d[6] w12 i/o ipd ddr_d[5] v12 i/o ipd ddr_d[4] v13 i/o ipd ddr_d[3] u13 i/o ipd ddr_d[2] v14 i/o ipd ddr_d[1] u14 i/o ipd ddr_d[0] u15 i/o ipd ddr_a[13] t5 o ipd ddr_a[12] v4 o ipd ddr_a[11] t4 o ipd ddr_a[10] w4 o ipd ddr_a[9] t6 o ipd ddr_a[8] u4 o ipd ddr_a[7] u6 o ipd ddr2 row/column address ddr_a[6] w5 o ipd ddr_a[5] v5 o ipd ddr_a[4] u5 o ipd ddr_a[3] v6 o ipd ddr_a[2] w6 o ipd ddr_a[1] t7 o ipd ddr_a[0] u7 o ipd ddr_clkp w8 o ipd ddr2 clock (positive) ddr_clkn w7 o ipd ddr2 clock (negative) ddr_cke v7 o ipd ddr2 clock enable ddr_we t8 o ipd ddr2 write enable ddr_ras w9 o ipd ddr2 row address strobe ddr_cas u9 o ipd ddr2 column address strobe ddr_cs v9 o ipd ddr2 chip select (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. 20 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 3-8. ddr2/mddr terminal functions (continued) signal type (1) pull (2) description name no. ddr_dqm[0] w13 o ipd ddr2 data mask outputs ddr_dqm[1] r10 o ipd ddr_dqs[0] t14 i/o ipd ddr2 data strobe inputs/outputs ddr_dqs[1] v11 i/o ipd ddr_ba[2] u8 o ipd ddr_ba[1] t9 o ipd ddr2 sdram bank address ddr_ba[0] v8 o ipd ddr2 loopback signal for external dqs gating. ddr_dqgate0 r11 o ipd route to ddr and back to ddr_dqgate1 with same constraints as used for ddr clock and data. ddr2 loopback signal for external dqs gating. ddr_dqgate1 r12 i ipd route to ddr and back to ddr_dqgate0 with same constraints as used for ddr clock and data. ddr2 reference output for drive strength calibration ddr_zp u12 o ? of n and p channel outputs. tie to ground via 50 ohm resistor @ 5% tolerance. ddr voltage input for the ddr2/mddr i/o buffers. ddr_vref r6 i ? note even in the case of mddr an external resistor divider connected to this pin is necessary. n10, p10, n9, p9, r9, p8, ddr_dvdd18 pwr ? ddr phy 1.8v power supply pins r8, p7, r7, n6 copyright ? 2010 ? 2014, texas instruments incorporated device overview 21 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.7 serial peripheral interface modules (spi) table 3-9. serial peripheral interface (spi) terminal functions signal power type (1) pull (2) description group (3) name no. spi0 spi0_clk / gp1[8] / mii_rxclk d19 i/o cp[7] a spi0 clock spi0_ena / mii_rxdv c17 i/o cp[7] a spi0 enable spi0_scs[0] / tm64p1_out12 / gp1[6] / mdio / tm64p1_in12 d17 i/o cp[10] a spi0_scs[1] / tm64p0_out12 / gp1[7] / mdclk / tm64p0_in12 e16 i/o cp[10] a spi0_scs[2] / uart0_rts / gp8[1] / mii_rxd[0] d16 i/o cp[9] a spi0 chip selects spi0_scs[3] / uart0_cts / gp8[2] / mii_rxd[1] e17 i/o cp[9] a spi0_scs[4] / uart0_txd / gp8[3] / mii_rxd[2] d18 i/o cp[8] a spi0_scs[5] / uart0_rxd / gp8[4] / mii_rxd[3] c19 i/o cp[8] a spi0 data slave-in- spi0_simo / gp8[5] / mii_crs c18 i/o cp[7] a master-out spi0 data slave-out- spi0_somi / gp8[6] / mii_rxer c16 i/o cp[7] a master-in spi1 spi1_clk / gp2[13] g19 i/o cp[15] a spi1 clock spi1_ena / gp2[12] h16 i/o cp[15] a spi1 enable spi1_scs[0] /gp2[14] / tm64p3_in12 e19 i/o cp[14] a spi1_scs[1] / gp2[15] / tm64p2_in12 f18 i/o cp[14] a spi1_scs[2] / uart1_txd / gp1[0] f19 i/o cp[13] a spi1_scs[3] / uart1_rxd / gp1[1] e18 i/o cp[13] a spi1 chip selects spi1_scs[4] / uart2_txd / gp1[2] f16 i/o cp[12] a spi1_scs[5] / uart2_rxd / gp1[3] f17 i/o cp[12] a spi1_scs[6] / i2c0_sda / tm64p3_out12 / gp1[4] g18 i/o cp[11] a spi1_scs[7] / i2c0_scl / tm64p2_out12 / gp1[5] g16 i/o cp[11] a spi1 data slave-in- spi1_simo / gp2[10] g17 i/o cp[15] a master-out spi1 data slave-out- spi1_somi / gp2[11] h17 i/o cp[15] a master-in (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 22 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7.8 boot table 3-10. boot mode selection terminal functions (1) signal power type (2) pull (3) description group (4) name no. gp7[7] / boot[7] p4 i cp[29] c gp7[6] / boot[6] r3 i cp[29] c gp7[5] / boot[5] r2 i cp[29] c gp7[4] / boot[4] r1 i cp[29] c boot mode selection pins gp7[3] / boot[3] t3 i cp[29] c gp7[2] / boot[2] t2 i cp[29] c gp7[1] / boot[1] t1 i cp[29] c gp7[0] / boot[0] u3 i cp[29] c (1) boot decoding is defined in the bootloader application report. (2) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (3) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (4) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. copyright ? 2010 ? 2014, texas instruments incorporated device overview 23 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.9 universal asynchronous receiver/transmitters (uart0, uart1, uart2) table 3-11. universal asynchronous receiver/transmitter (uart) terminal functions signal power type (1) pull (2) description group (3) name no. uart0 spi0_scs[5] / uart0_rxd / gp8[4] / mii_rxd[3] c19 i cp[8] a uart0 receive data spi0_scs[4] / uart0_txd / gp8[3] / mii_rxd[2] d18 o cp[8] a uart0 transmit data spi0_scs[2] / uart0_rts / gp8[1] d16 o cp[9] a uart0 ready-to-send output spi0_scs[3] / uart0_cts / gp8[2] e17 i cp[9] a uart0 clear-to-send input uart1 spi1_scs[3] / uart1_rxd / gp1[1] e18 i cp[13] a uart1 receive data spi1_scs[2] / uart1_txd / gp1[0] f19 o cp[13] a uart1 transmit data ahclkr / uart1_rts / gp0[11] a2 o cp[0] a uart1 ready-to-send output ahclkx / usb_refclkin / uart1_cts / gp0[10] a3 i cp[0] a uart1 clear-to-send input uart2 spi1_scs[5] / uart2_rxd / gp1[3] f17 i cp[12] a uart2 receive data spi1_scs[4] / uart2_txd / gp1[2] f16 o cp[12] a uart2 transmit data amute / uart2_rts / gp0[9] d5 o cp[0] a uart2 ready-to-send output rtc_alarm / uart2_cts / gp0[8] / deepsleep f4 i cp[0] a uart2 clear-to-send input (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module.the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 24 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7.10 inter-integrated circuit modules (i2c0) table 3-12. inter-integrated circuit (i2c) terminal functions signal power type (1) pull (2) description group (3) name no. i2c0 spi1_scs[6] / i2c0_sda / tm64p3_out12 / gp1[4] g18 i/o cp[11] a i2c0 serial data spi1_scs[7] / i2c0_scl / tm64p2_out12 / gp1[5] g16 i/o cp[11] a i2c0 serial clock (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module.the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. copyright ? 2010 ? 2014, texas instruments incorporated device overview 25 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.11 timers table 3-13. timers terminal functions signal power type (1) pull (2) description group (3) name no. timer0 spi0_scs[1] / tm64p0_out12 / gp1[7] / mdclk / tm64p0_in12 e16 i cp[10] a timer0 lower input timer0 lower spi0_scs[1] / tm64p0_out12 / gp1[7] / mdclk / tm64p0_in12 e16 o cp[10] a output timer1 (watchdog) spi0_scs[0] / tm64p1_out12 / gp1[6] / mdio / tm64p1_in12 d17 i cp[10] a timer1 lower input timer1 lower spi0_scs[0] / tm64p1_out12 / gp1[6] / mdio /tm64p1_in12 d17 o cp[10] a output timer2 spi1_scs[1] / gp2[15] / tm64p2_in12 f18 i cp[14] a timer2 lower input timer2 lower spi1_scs[7] / i2c0_scl / tm64p2_out12 / gp1[5] g16 o cp[11] a output timer3 spi1_scs[0] / gp2[14] / tm64p3_in12 e19 i cp[14] a timer3 lower input timer3 lower spi1_scs[6] / i2c0_sda / tm64p3_out12 / gp1[4] g18 o cp[11] a output (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 26 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7.12 multichannel audio serial ports (mcasp) table 3-14. multichannel audio serial ports terminal functions signal power type (1) pull (2) description group (3) name no. mcasp0 axr15 / gp0[7] a4 i/o cp[1] a axr14 / gp0[6] b4 i/o cp[2] a axr13 / gp0[5] b3 i/o cp[2] a axr12 / gp0[4] c4 i/o cp[2] a axr11 / gp0[3] c5 i/o cp[2] a axr10 / gp0[2] d4 i/o cp[2] a axr9 / gp0[1] c3 i/o cp[2] a axr8 / gp0[0] e4 i/o cp[3] a mcasp0 serial data axr7 / gp1[15] d2 i/o cp[4] a axr6 / gp1[14] / mii_txen c1 i/o cp[5] a axr5 / gp1[13] / mii_txclk d3 i/o cp[5] a axr4 / gp1[12] / mii_col d1 i/o cp[5] a axr3 / gp1[11] / mii_txd[3] e3 i/o cp[5] a axr2 / gp1[10] / mii_txd[2] e2 i/o cp[5] a axr1 / gp1[9] / mii_txd[1] e1 i/o cp[5] a axr0 / gp8[7] / mii_txd[0] f3 i/o cp[6] a ahclkx / usb_refclkin / uart1_cts / gp0[10] a3 i/o cp[0] a mcasp0 transmit master clock aclkx / gp0[14] b1 i/o cp[0] a mcasp0 transmit bit clock afsx / gp0[12] b2 i/o cp[0] a mcasp0 transmit frame sync ahclkr / uart1_rts /gp0[11] a2 i/o cp[0] a mcasp0 receive master clock aclkr / gp0[15] a1 i/o cp[0] a mcasp0 receive bit clock afsr / gp0[13] c2 i/o cp[0] a mcasp0 receive frame sync amute / uart2_rts / gp0[9] d5 i/o cp[0] a mcasp0 mute output (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. copyright ? 2010 ? 2014, texas instruments incorporated device overview 27 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.13 universal serial bus modules (usb0) table 3-15. universal serial bus (usb) terminal functions signal power type (1) pull (2) description group (3) name no. usb0 2.0 otg (usb0) usb0_dm m18 a ipd ? usb0 phy data minus usb0_dp m19 a ipd ? usb0 phy data plus usb0_vdda33 n18 pwr ? ? usb0 phy 3.3-v supply usb0 phy identification usb0_id p16 a ? ? (mini-a or mini-b plug) usb0_vbus n19 a ? ? usb0 bus voltage usb0_drvvbus k18 o ipd b usb0 controller vbus control output. ahclkx / usb_refclkin / uart1_cts / a3 i cp[0] a usb_refclkin. optional clock input gp0[10] usb0_vdda18 n14 pwr ? ? usb0 phy 1.8-v supply input usb0 phy 1.2-v ldo output for bypass cap for proper device operation, this pin must usb0_vdda12 n17 a ? ? always be connected via a 0.22- f capacitor to vss (gnd), even if usb0 is not being used. usb_cvdd m12 pwr ? ? usb0 core logic 1.2-v supply input (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 28 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7.14 ethernet media access controller (emac) table 3-16. ethernet media access controller (emac) terminal functions signal power type (1) pull (2) description group (3) name no. mii axr6 / gp1[14] / mii_txen c1 o cp[5] a emac mii transmit enable output axr5 / gp1[13] / mii_txclk d3 i cp[5] a emac mii transmit clock input axr4 / gp1[12] / mii_col d1 i cp[5] a emac mii collision detect input axr3 / gp1[11] / mii_txd[3] e3 o cp[5] a axr2 / gp1[10] / mii_txd[2] e2 o cp[5] a emac mii transmit data axr1 / gp1[9] / mii_txd[1] e1 o cp[5] a axr0 / gp8[7] / mii_txd[0] f3 o cp[6] a spi0_somi / gp8[6] / mii_rxer c16 i cp[7] a emac mii receive error input spi0_simo / gp8[5] / mii_crs c18 i cp[7] a emac mii carrier sense input spi0_clk / gp1[8] / mii_rxclk d19 i cp[7] a emac mii receive clock input spi0_ena / mii_rxdv c17 i cp[7] a emac mii receive data valid input spi0_scs[5] / uart0_rxd / gp8[4] / mii_rxd[3] c19 i cp[8] a spi0_scs[4] / uart0_txd / gp8[3] / mii_rxd[2] d18 i cp[8] a emac mii receive data spi0_scs[3] / uart0_cts / gp8[2] / mii_rxd[1] e17 i cp[9] a spi0_scs[2] / uart0_rts / gp8[1] / mii_rxd[0] d16 i cp[9] a rmii rmii_mhz_50_clk w18 i/o cp[26] c emac 50-mhz clock input or output rmii_rxer w17 i cp[26] c emac rmii receiver error rmii_rxd[0] v17 i cp[26] c emac rmii receive data rmii_rxd[1] w16 i cp[26] c rmii_crs_dv w19 i cp[26] c emac rmii carrier sense data valid rmii_txen r14 o cp[26] c emac rmii transmit enable rmii_txd[0] v16 o cp[26] c emac rmii transmit data rmii_txd[1] u18 o cp[26] c mdio spi0_scs[0] / tm64p1_out12 / gp1[6] / mdio / d17 i/o cp[10] a mdio serial data tm64p1_in12 spi0_scs[1] / tm64p0_out12 / gp1[7] / mdclk / e16 o cp[10] a mdio clock tm64p0_in12 (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. copyright ? 2010 ? 2014, texas instruments incorporated device overview 29 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.15 multimedia card/secure digital (mmc/sd) table 3-17. multimedia card/secure digital (mmc/sd) terminal functions signal power type (1) pull (2) description group (3) name no. mmcsd0 mmcsd0_clk / gp4[7] e9 o cp[18] b mmcsd0 clock ema_a[22] / mmcsd0_cmd / gp4[6] a10 i/o cp[18] b mmcsd0 command ema_a[14] / mmcsd0_dat[7] / gp5[14] a12 i/o cp[19] b ema_a[15] / mmcsd0_dat[6] / gp5[15] c11 i/o cp[19] b ema_a[16] / mmcsd0_dat[5] / gp4[0] e12 i/o cp[18] b ema_a[17] / mmcsd0_dat[4] / gp4[1] b11 i/o cp[18] b mmc/sd0 data ema_a[18] / mmcsd0_dat[3] / gp4[2] e11 i/o cp[18] b ema_a[19] / mmcsd0_dat[2] / gp4[3] c10 i/o cp[18] b ema_a[20] / mmcsd0_dat[1] / gp4[4] a11 i/o cp[18] b ema_a[21] / mmcsd0_dat[0] / gp4[5] b10 i/o cp[18] b (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. 30 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7.16 general purpose input output table 3-18. general purpose input output terminal functions signal power type (1) pull (2) description group (3) name no. gp0 aclkr / gp0[15] a1 i/o cp[0] a aclkx / gp0[14] b1 i/o cp[0] a afsr / gp0[13] c2 i/o cp[0] a afsx / gp0[12] b2 i/o cp[0] a ahclkr / uart1_rts / gp0[11] a2 i/o cp[0] a ahclkx / usb_refclkin / uart1_cts / gp0[10] a3 i/o cp[0] a amute / uart2_rts / gp0[9] d5 i/o cp[0] a rtc_alarm / uart2_cts / gp0[8] / deepsleep f4 i/o cp[0] a gpio bank 0 axr15 / gp0[7] a4 i/o cp[1] a axr14 / gp0[6] b4 i/o cp[2] a axr13 / gp0[5] b3 i/o cp[2] a axr12 / gp0[4] c4 i/o cp[2] a axr11 / gp0[3] c5 i/o cp[2] a axr10 / gp0[2] d4 i/o cp[2] a axr9 / gp0[1] c3 i/o cp[2] a axr8 / gp0[0] e4 i/o cp[3] a (1) i = input, o = output, i/o = bidirectional, z = high impedance, pwr = supply voltage, gnd = ground, a = analog signal. note: the pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. all multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-z operation. all gpio signals can be used as input or output. for multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) ipd = internal pulldown resistor; ipu = internal pullup resistor; cp[ n ] = configurable pull-up/pull-down (where n is the pin group) using the pupdena and pupdsel registers in the system module. the pull-up and pull-down control of these pins is not active until the device is out of reset. during reset, all of the pins associated with these registers are pulled down. if the application requires a pull-up, an external pull-up can be used. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the device configuration section. for electrical specifications on pullup and internal pulldown circuits, see the device operating conditions section. (3) this signal is part of a dual-voltage io group (a, b or c). these groups can be operated at 3.3v or 1.8v nominal. the three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. group a operates at the voltage of power supply dvdd3318_a. group b operates at the voltage of power supply dvdd3318_b. group c operates at the voltage of power supply dvdd3318_c. copyright ? 2010 ? 2014, texas instruments incorporated device overview 31 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 3-18. general purpose input output terminal functions (continued) signal power type (1) pull (2) description group (3) name no. gp1 axr7 / gp1[15] d2 i/o cp[4] a axr6 / gp1[14] / mii_txen c1 i/o cp[5] a axr5 / gp1[13] / mii_txclk d3 i/o cp[5] a axr4 / gp1[12] / mii_col d1 i/o cp[5] a axr3 / gp1[11] / mii_txd[3] e3 i/o cp[5] a axr2 / gp1[10] / mii_txd[2] e2 i/o cp[5] a axr1 / gp1[9] / mii_txd[1] e1 i/o cp[5] a spi0_clk / gp1[8] / mii_rxclk d19 i/o cp[7] a gpio bank 1 spi0_scs[1] / tm64p0_out12 / gp1[7] / mdclk / tm64p0_in12 e16 i/o cp[10] a spi0_scs[0] / tm64p1_out12 / gp1[6] / mdio / tm64p1_in12 d17 i/o cp[10] a spi1_scs[7] / i2c0_scl / tm64p2_out12 / gp1[5] g16 i/o cp[11] a spi1_scs[6] / i2c0_sda / tm64p3_out12 / gp1[4] g18 i/o cp[11] a spi1_scs[5] / uart2_rxd / gp1[3] f17 i/o cp[12] a spi1_scs[4] / uart2_txd / gp1[2] f16 i/o cp[12] a spi1_scs[3] / uart1_rxd / gp1[1] e18 i/o cp[13] a spi1_scs[2] / uart1_txd / gp1[0] f19 i/o cp[13] a gp2 spi1_scs[1] / gp2[15] / tm64p2_in12 f18 i/o cp[14] a spi1_scs[0] / gp2[14] / tm64p3_in12 e19 i/o cp[14] a spi1_clk / gp2[13] g19 i/o cp[15] a spi1_ena / gp2[12] h16 i/o cp[15] a spi1_somi / gp2[11] h17 i/o cp[15] a spi1_simo / gp2[10] g17 i/o cp[15] a ema_ba[1] / gp2[9] a15 i/o cp[16] b ema_ba[0] / gp2[8] c15 i/o cp[16] b gpio bank 2 ema_clk / gp2[7] b7 i/o cp[16] b ema_sdcke / gp2[6] d8 i/o cp[16] b ema_ras / gp2[5] a16 i/o cp[16] b ema_cas / gp2[4] a9 i/o cp[16] b ema_wen_dqm[0] / gp2[3] c8 i/o cp[16] b ema_wen_dqm[1] / gp2[2] a5 i/o cp[16] b ema_wait[1] / gp2[1] b19 i/o cp[16] b ema_cs[0] / gp2[0] a18 i/o cp[16] b 32 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 3-18. general purpose input output terminal functions (continued) signal power type (1) pull (2) description group (3) name no. gp3 ema_cs[2] / gp3[15] b17 i/o cp[16] b ema_cs[3] / gp3[14] a17 i/o cp[16] b ema_cs[4] / gp3[13] f9 i/o cp[16] b ema_cs[5] / gp3[12] b16 i/o cp[16] b ema_we / gp3[11] b9 i/o cp[16] b ema_oe / gp3[10] b15 i/o cp[16] b ema_a_r w / gp3[9] d10 i/o cp[16] b ema_wait[0] / gp3[8] b18 i/o cp[16] b gpio bank 3 ema_d[15] / gp3[7] e6 i/o cp[17] b ema_d[14] / gp3[6] c7 i/o cp[17] b ema_d[13] / gp3[5] b6 i/o cp[17] b ema_d[12] / gp3[4] a6 i/o cp[17] b ema_d[11] / gp3[3] d6 i/o cp[17] b ema_d[10] / gp3[2] a7 i/o cp[17] b ema_d[9] / gp3[1] d9 i/o cp[17] b ema_d[8] / gp3[0] e10 i/o cp[17] b gp4 ema_d[7] / gp4[15] d7 i/o cp[17] b ema_d[6] / gp4[14] c6 i/o cp[17] b ema_d[5] / gp4[13] e7 i/o cp[17] b ema_d[4] / gp4[12] b5 i/o cp[17] b ema_d[3] / gp4[11] e8 i/o cp[17] b ema_d[2] / gp4[10] b8 i/o cp[17] b ema_d[1] / gp4[9] a8 i/o cp[17] b ema_d[0] / gp4[8] c9 i/o cp[17] b gpio bank 4 mmcsd0_clk / gp4[7] e9 i/o cp[18] b ema_a[22] / mmcsd0_cmd / gp4[6] a10 i/o cp[18] b ema_a[21] / mmcsd0_dat[0] / gp4[5] b10 i/o cp[18] b ema_a[20] / mmcsd0_dat[1] / gp4[4] a11 i/o cp[18] b ema_a[19] / mmcsd0_dat[2] / gp4[3] c10 i/o cp[18] b ema_a[18] / mmcsd0_dat[3] / gp4[2] e11 i/o cp[18] b ema_a[17] / mmcsd0_dat[4] / gp4[1] b11 i/o cp[18] b ema_a[16] / mmcsd0_dat[5] / gp4[0] e12 i/o cp[18] b copyright ? 2010 ? 2014, texas instruments incorporated device overview 33 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 3-18. general purpose input output terminal functions (continued) signal power type (1) pull (2) description group (3) name no. gp5 ema_a[15] / mmcsd0_dat[6] / gp5[15] c11 i/o cp[19] b ema_a[14] / mmcsd0_dat[7] / gp5[14] a12 i/o cp[19] b ema_a[13] / gp5[13] d11 i/o cp[19] b ema_a[12] / gp5[12] d13 i/o cp[19] b ema_a[11] / gp5[11] b12 i/o cp[19] b ema_a[10] / gp5[10] c12 i/o cp[19] b ema_a[9] / gp5[9] d12 i/o cp[19] b ema_a[8] / gp5[8] a13 i/o cp[19] b gpio bank 5 ema_a[7] / gp5[7] b13 i/o cp[20] b ema_a[6] / gp5[6] e13 i/o cp[20] b ema_a[5] / gp5[5] c13 i/o cp[20] b ema_a[4] / gp5[4] a14 i/o cp[20] b ema_a[3] / gp5[3] d14 i/o cp[20] b ema_a[2] / gp5[2] b14 i/o cp[20] b ema_a[1] / gp5[1] d15 i/o cp[20] b ema_a[0] / gp5[0] c14 i/o cp[20] b gp6 resetout / gp6[15] t17 i/o cp[21] c clkout / gp6[14] t18 i/o cp[22] c gp6[13] r17 i/o cp[23] c gp6[12] r16 i/o cp[23] c gp6[11] u17 i/o cp[24] c gp6[10] w15 i/o cp[24] c gp6[9] u16 i/o cp[24] c gp6[8] t15 i/o cp[24] c gpio bank 6 gp6[7] w14 i/o cp[25] c gp6[6] v15 i/o cp[25] c gp6[5] p17 i/o cp[27] c gp6[4] h3 i/o cp[30] c gp6[3] k3 i/o cp[30] c gp6[2] j3 i/o cp[30] c gp6[1] k4 i/o cp[30] c gp6[0] r5 i/o cp[31] c 34 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 3-18. general purpose input output terminal functions (continued) signal power type (1) pull (2) description group (3) name no. gp7 gp7[15] u2 i/o cp[28] c gp7[14] u1 i/o cp[28] c gp7[13] v3 i/o cp[28] c gp7[12] v2 i/o cp[28] c gp7[11] v1 i/o cp[28] c gp7[10] w3 i/o cp[28] c gp7[9] w2 i/o cp[28] c gp7[8] w1 i/o cp[28] c gpio bank 7 gp7[7] / boot[7] p4 i/o cp[29] c gp7[6] / boot[6] r3 i/o cp[29] c gp7[5] / boot[5] r2 i/o cp[29] c gp7[4] / boot[4] r1 i/o cp[29] c gp7[3] / boot[3] t3 i/o cp[29] c gp7[2] / boot[2] t2 i/o cp[29] c gp7[1] / boot[1] t1 i/o cp[29] c gp7[0] / boot[0] u3 i/o cp[29] c gp8 gp8[15] g1 i/o cp30] c gp8[14] g2 i/o cp[30] c gp8[13] j4 i/o cp[30] c gp8[12] g3 i/o cp[30] c gp8[11] f1 i/o cp[31] c gp8[10] f2 i/o cp[31] c gp8[9] h4 i/o cp[31] c gp8[8] g4 i/o cp[31] c gpio bank 8 axr0 / gp8[7] / mii_txd[0] f3 i/o cp[6] a spi0_somi / gp8[6] / mii_rxer c16 i/o cp[7] a spi0_simo / gp8[5] / mii_cr c18 i/o cp[7] a spi0_scs[5] / uart0_rxd / gp8[4] / mii_rxd[3] c19 i/o cp[8] a spi0_scs[4] / uart0_txd / gp8[3] / mii_rxd[2] d18 i/o cp[8] a spi0_scs[3] / uart0_cts / gp8[2] / mii_rxd[1] e17 i/o cp[9] a spi0_scs[2] / uart0_rts / gp8[1] / mii_rxd[0] d16 i/o cp[9] a rtck / gp8[0] (1) k17 i/o ipd b (1) gp8[0] is initially configured as a reserved function after reset and will not be in a predictable state. this signal will only be stable after the gpio configuration for this pin has been completed. users should carefully consider the system implications of this pin being in an unknown state after reset. copyright ? 2010 ? 2014, texas instruments incorporated device overview 35 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 3.7.17 reserved and no connect table 3-19. reserved and no connect terminal functions signal type (1) description name no. reserved. for proper device operation, this pin must be tied either directly to rsv2 t19 pwr cvdd or left unconnected (do not connect to ground). nc_j1 j1 ? nc_j2 j2 ? nc_l1 l1 ? nc_l2 l2 ? nc_m2 m2 ? nc_m3 m3 ? nc_m14 m14 ? nc_n1 n1 ? nc_n2 n2 ? nc_n3 n3 ? nc_n4 n4 ? nc_n16 n16 ? nc_p1 p1 ? these signals should be left unconnected (do not connect to connect to power or ground). nc_p2 p2 ? nc_p3 p3 ? nc_p14 p14 ? nc_p15 p15 ? nc_p18 p18 ? nc_p19 p19 ? nc_r15 r15 ? nc_r18 r18 ? nc_r19 r19 ? nc_t16 t16 ? nc_u19 u19 ? nc_v18 v18 ? nc_v19 v19 ? reserved. for proper device operation, the pin must be pulled up to supply rsvdn j17 i dvdd3318_b. (1) pwr = supply voltage. 36 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 3.7.18 supply and ground table 3-20. supply and ground terminal functions signal type (1) description name no. e15, g7, g8, g13, h6, h7, h10, h11, cvdd (core supply) h12, h13, j6, pwr variable (1.2v - 1.0v) core supply voltage pins j12, k6, k12, l12, m8, m9, n8 rvdd (internal ram supply) e5, h14, n7 pwr 1.2v internal ram supply voltage pins f14, g6, g10, g11, g12, 1.8v i/o supply voltage pins. dvdd18 must be powered even if all of dvdd18 (i/o supply) pwr j13, k5, l6, the dvdd3318_x supplies are operated at 3.3v. p13, r13 f5, f15, g5, dvdd3318_a (i/o supply) pwr 1.8v or 3.3-v dual-voltage lvcmos i/o supply voltage pins, group a g14, g15, h5 e14, f6, f7, f8, f10, f11, dvdd3318_b (i/o supply) pwr 1.8v or 3.3-v dual-voltage lvcmos i/o supply voltage pins, group b f12, f13, g9, j14, k15 j5, k13, l4, l13, m13, dvdd3318_c (i/o supply) pwr 1.8v or 3.3-v dual-voltage lvcmos i/o supply voltage pins, group c n13, p5, p6, p12, r4 a19, h1, h2, h8, h9, h15, j7, j8, j9, j10, j11, k1, k2, k7, k8, k9, k10, k11, l3, vss (ground) gnd ground pins. l5, l7, l8, l9, l10, l11, m1, m4, m5, m6, m7, m10, m11, n5, n11, n12, p11 usb0_vdda33 n18 pwr usb0 phy 3.3-v supply usb0_vdda18 n14 pwr usb0 phy 1.8-v supply input usb0_vdda12 n17 a usb0 phy 1.2-v ldo output for bypass cap usb_cvdd m12 pwr usb0 core logic 1.2-v supply input n10, p10, n9, ddr_dvdd18 p9, r9, p8, pwr ddr phy 1.8v power supply pins r8, p7, r7, n6 (1) pwr = supply voltage, gnd - ground. 3.8 unused pin configurations all signals multiplexed with multiple functions may be used as an alternate function if a given peripheral is not used. unused non-multiplexed signals and some other specific signals should be handled as specified in the tables below. table 3-21. unused usb0 signal configurations signal name configuration (when usb0 is not used) usb0_dm no connect usb0_dp no connect usb0_id no connect usb0_vbus no connect copyright ? 2010 ? 2014, texas instruments incorporated device overview 37 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 3-21. unused usb0 signal configurations (continued) signal name configuration (when usb0 is not used) usb0_drvvbus no connect usb0_vdda33 no connect usb0_vdda18 no connect usb0_vdda12 internal usb phy output connected to an external 0.22- f filter capacitor usb_refclkin no connect or other peripheral function usb_cvdd 1.2v table 3-22. unused rtc signal configuration signal name configuration rtc_xi may be held high (cvdd) or low rtc_xo no connect rtc_alarm may be used as gpio or other peripheral function rtc_cvdd connect to cvdd rtc_vss vss table 3-23. unused ddr2/mddr controller signal configuration signal name configuration (1) ddr_d[15:0] no connect ddr_a[13:0] no connect ddr_clkp no connect ddr_clkn no connect ddr_cke no connect ddr_we no connect ddr_ras no connect ddr_cas no connect dds_cs no connect ddr_dqm[1:0] no connect ddr_dqs[1:0] no connect ddr_ba[2:0] no connect ddr_dqgate0 no connect ddr_dqgate1 no connect ddr_zp no connect ddr_vref no connect ddr_dvdd18 no connect (1) the ddr2/mddr input buffers are enabled by default on device power up and a maximum current draw of 25ma can result on the 1.8v supply. to minimize power consumption, the ddr2/mddr controller input receivers should be placed in power-down mode by setting vtpio[14] = 1. 38 device overview copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 4 device configuration 4.1 boot modes this device supports a variety of boot modes through an internal arm rom bootloader. this device does not support dedicated hardware boot modes. the input states of the boot pins are sampled and latched into the bootcfg register, which is part of the system configuration (syscfg) module, when device reset is deasserted. boot mode selection is determined by the values of the boot pins. see using the omap-l1x8 bootloader application report (sprab41) for more details on the rom boot loader. the following boot modes are supported: ? nand flash boot ? 8-bit nand ? 16-bit nand (supported on rom revisions after d800k002 -- see the bootloader documents mentioned above to determine the rom revision) ? nor flash boot ? nor direct boot (8-bit or 16-bit) ? nor legacy boot (8-bit or 16-bit) ? nor ais boot (8-bit or 16-bit) ? i2c0 boot ? eeprom (master mode) ? external host (slave mode) ? spi0/ spi1 boot ? serial flash (master mode) ? serial eeprom (master mode) ? external host (slave mode) ? uart0/uart1/uart2 boot ? external host ? mmc/sd0 boot 4.2 syscfg module the following system level features of the chip are controlled by the syscfg peripheral: ? readable device, die, and chip revision id ? control of pin multiplexing ? priority of bus accesses different bus masters in the system ? capture at power on reset the chip boot pin values and make them available to software ? control of the deepsleep power management function ? enable and selection of the programmable pin pullups and pulldowns ? special case settings for peripherals: ? locking of pll controller settings ? default burst sizes for edma3 transfer controllers ? mcasp amutein selection and clearing of amute status for the mcasp ? control of the reference clock source and other side-band signals for both of the integrated usb phys ? clock source selection for emifa ? ddr2 controller phy settings ? selects the source of emulation suspend signal (from arm) of peripherals supporting this function. copyright ? 2010 ? 2014, texas instruments incorporated device configuration 39 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com many registers are accessible only by a host (arm) when it is operating in its privileged mode. (ex. from the kernel, but not from user space code). table 4-1. system configuration (syscfg) module register access register address register name register description register access 0x01c1 4000 revid revision identification register ? 0x01c14008 dieidr0 device identification register 0 ? 0x01c1400c dieidr1 device identification register 1 ? 0x01c14010 dieidr2 device identification register 2 ? 0x01c14014 dieidr3 device identification register 3 ? 0x01c1 4020 bootcfg boot configuration register privileged mode 0x01c1 4038 kick0r kick 0 register privileged mode 0x01c1 403c kick1r kick 1 register privileged mode 0x01c1 4040 host0cfg host 0 configuration register ? 0x01c1 4044 host1cfg host 1 configuration register ? 0x01c1 40e0 irawstat interrupt raw status/set register privileged mode 0x01c1 40e4 ienstat interrupt enable status/clear register privileged mode 0x01c1 40e8 ienset interrupt enable register privileged mode 0x01c1 40ec ienclr interrupt enable clear register privileged mode 0x01c1 40f0 eoi end of interrupt register privileged mode 0x01c1 40f4 fltaddrr fault address register privileged mode 0x01c1 40f8 fltstat fault status register ? 0x01c1 4110 mstpri0 master priority 0 registers privileged mode 0x01c1 4114 mstpri1 master priority 1 registers privileged mode 0x01c1 4118 mstpri2 master priority 2 registers privileged mode 0x01c1 4120 pinmux0 pin multiplexing control 0 register privileged mode 0x01c1 4124 pinmux1 pin multiplexing control 1 register privileged mode 0x01c1 4128 pinmux2 pin multiplexing control 2 register privileged mode 0x01c1 412c pinmux3 pin multiplexing control 3 register privileged mode 0x01c1 4130 pinmux4 pin multiplexing control 4 register privileged mode 0x01c1 4134 pinmux5 pin multiplexing control 5 register privileged mode 0x01c1 4138 pinmux6 pin multiplexing control 6 register privileged mode 0x01c1 413c pinmux7 pin multiplexing control 7 register privileged mode 0x01c1 4140 pinmux8 pin multiplexing control 8 register privileged mode 0x01c1 4144 pinmux9 pin multiplexing control 9 register privileged mode 0x01c1 4148 pinmux10 pin multiplexing control 10 register privileged mode 0x01c1 414c pinmux11 pin multiplexing control 11 register privileged mode 0x01c1 4150 pinmux12 pin multiplexing control 12 register privileged mode 0x01c1 4154 pinmux13 pin multiplexing control 13 register privileged mode 0x01c1 4158 pinmux14 pin multiplexing control 14 register privileged mode 0x01c1 415c pinmux15 pin multiplexing control 15 register privileged mode 0x01c1 4160 pinmux16 pin multiplexing control 16 register privileged mode 0x01c1 4164 pinmux17 pin multiplexing control 17 register privileged mode 0x01c1 4168 pinmux18 pin multiplexing control 18 register privileged mode 0x01c1 416c pinmux19 pin multiplexing control 19 register privileged mode 0x01c1 4170 suspsrc suspend source register privileged mode 0x01c1 4174 reserved ? 0x01c1 4178 reserved ? 0x01c1 417c cfgchip0 chip configuration 0 register privileged mode 40 device configuration copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 4-1. system configuration (syscfg) module register access (continued) register address register name register description register access 0x01c1 4180 cfgchip1 chip configuration 1 register privileged mode 0x01c1 4184 cfgchip2 chip configuration 2 register privileged mode 0x01c1 4188 cfgchip3 chip configuration 3 register privileged mode 0x01c1 418c cfgchip4 chip configuration 4 register privileged mode 0x01e2 c000 vtpio_ctl vtpio control register privileged mode 0x01e2 c004 ddr_slew ddr slew register privileged mode 0x01e2 c008 deepsleep deepsleep register privileged mode 0x01e2 c00c pupd_ena pullup / pulldown enable register privileged mode 0x01e2 c010 pupd_sel pullup / pulldown selection register privileged mode 0x01e2 c014 rxactive rxactive control register privileged mode 0x01e2 c018 pwrdn pwrdn control register privileged mode copyright ? 2010 ? 2014, texas instruments incorporated device configuration 41 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 4.3 pullup/pulldown resistors proper board design should ensure that input pins to the device always be at a valid logic level and not floating. this may be achieved via pullup/pulldown resistors. the device features internal pullup (ipu) and internal pulldown (ipd) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. an external pullup/pulldown resistor needs to be used in the following situations: ? boot and configuration pins: if the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the ipu/ipd matches the desired value/state. ? other input pins: if the ipu/ipd does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. for the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. in addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. tips for choosing an external pullup/pulldown resistor: ? consider the total amount of current that may pass through the pullup or pulldown resistor. make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. ? decide a target value for the net. for a pulldown resistor, this should be below the lowest v il level of all inputs connected to the net. for a pullup resistor, this should be above the highest v ih level of all inputs on the net. a reasonable choice would be to target the v ol or v oh levels for the logic family of the limiting device; which, by definition, have margin to the v il and v ih levels. ? select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. the current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. ? for bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). ? remember to include tolerances when selecting the resistor value. ? for pullup resistors, also remember to include tolerances on the io supply rail. ? for most systems, a 1-k ? resistor can be used to oppose the ipu/ipd while meeting the above criteria. users should confirm this resistor value is correct for their specific application. ? for most systems, a 20-k ? resistor can be used to compliment the ipu/ipd on the boot and configuration pins while meeting the above criteria. users should confirm this resistor value is correct for their specific application. ? for more detailed information on input current (i i ), and the low-/high-level input voltages (v il and v ih ) for the device, see section 5.3 , recommended operating conditions. ? for the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table. 42 device configuration copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 5 specifications 5.1 absolute maximum ratings over operating junction temperature range (unless otherwise noted) (1) core logic, variable and fixed -0.5 v to 1.4 v (cvdd, rvdd, rtc_cvdd, pll0_vdda , pll1_vdda , usb_cvdd ) (2) supply voltage ranges i/o, 1.8v -0.5 v to 2 v (usb0_vdda18, ddr_dvdd18) (2) i/o, 3.3v -0.5 v to 3.8v (dvdd3318_a, dvdd3318_b, dvdd3318_c, usb0_vdda33) (2) oscillator inputs (oscin, rtc_xi), 1.2v -0.3 v to cvdd + 0.3v dual-voltage lvcmos inputs, 3.3v or 1.8v (steady state) -0.3v to dvdd + 0.3v dual-voltage lvcmos inputs, operated as 3.3v dvdd + 20% (transient overshoot/undershoot) up to 20% of signal period input voltage (v i ) ranges dual-voltage lvcmos inputs, operated as 1.8v dvdd + 30% (transient overshoot/undershoot) up to 30% of signal period usb 5v tolerant ios: 5.25v (3) (usb0_dm, usb0_dp, usb0_id) usb0 vbus pin 5.50v (3) dual-voltage lvcmos outputs, 3.3v or 1.8v -0.3 v to dvdd + 0.3v (steady state) dual-voltage lvcmos outputs, operated as 3.3v dvdd + 20% (transient overshoot/undershoot) up to 20% of signal output voltage (v o ) ranges period dual-voltage lvcmos outputs, operated as 1.8v dvdd + 30% (transient overshoot/undershoot) up to 30% of signal period input or output voltages 0.3v above or below their respective power 20ma clamp current rails. limit clamp current that flows through the i/o's internal diode protection cells. operating junction temperature ranges, industrial -40 c to 90 c t j (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to vss, usb0_vssa33, usb0_vssa, pll0_vssa, oscvss, rtc_vss (3) up to a maximum of 24 hours. 5.2 handling ratings min max unit storage temperature range, t stg (default) -55 150 c human body model (hbm) (2) > 1 > 1 kv esd stress voltage, v esd (1) charged device model (cdm) (3) > 500 > 500 v (1) electrostatic discharge (esd) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. (2) level listed above is the passing level per ansi/esda/jedec js-001-2010. jedec document jep 155 states that 500v hbm allows safe manufacturing with a standard esd control process, and manufacturing with less than 500v hbm is possible if necessary precautions are taken. pins listed as 1000v may actually have higher performance. (3) level listed above is the passing level per eia-jedec jesd22-c101e. jedec document jep 157 states that 250v cdm allows safe manufacturing with a standard esd control process. pins listed as 250v may actually have higher performance. copyright ? 2010 ? 2014, texas instruments incorporated specifications 43 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 5.3 recommended operating conditions name description condition min nom max unit cvdd core logic supply voltage (variable) 1.2v operating point 1.14 1.2 1.32 v 1.1v operating point 1.05 1.1 1.16 v 1.0v operating point 0.95 1.0 1.05 v rvdd internal ram supply voltage 300 mhz versions 1.14 1.2 1.32 v rtc_cvdd (1) rtc core logic supply voltage 0.9 1.2 1.32 v pll0_vdda pll0 supply voltage 1.14 1.2 1.32 v pll1_vdda pll1 supply voltage 1.14 1.2 1.32 v usb_cvdd usb0 core logic supply voltage 1.14 1.2 1.32 v usb0_vdda18 usb0 phy supply voltage 1.71 1.8 1.89 v usb0_vdda33 usb0 phy supply voltage 3.15 3.3 3.45 v supply dvdd18 (2) 1.8v logic supply 1.71 1.8 1.89 v voltage ddr_dvdd18 ddr2 phy supply voltage 1.71 1.8 1.89 v (2) 0.49* 0.5* 0.51* ddr_vref ddr2/mddr reference voltage v ddr_dvdd18 ddr_dvdd18 ddr_dvdd18 ddr2/mddr impedance control, ddr_zp vss v connected via 50 ? resistor to vss 1.8v operating point 1.71 1.8 1.89 v power group a dual-voltage io dvdd3318_a supply voltage 3.3v operating point 3.15 3.3 3.45 v 1.8v operating point 1.71 1.8 1.89 v power group b dual-voltage io dvdd3318_b supply voltage 3.3v operating point 3.15 3.3 3.45 v 1.8v operating point 1.71 1.8 1.89 v power group c dual-voltage io dvdd3318_c supply voltage 3.3v operating point 3.15 3.3 3.45 v supply vss core logic digital ground v ground pll0_vssa pll0 ground v pll1_vssa pll1 ground v oscvss (3) oscillator ground v rtc_vss (3) rtc oscillator ground v usb0_vssa usb0 phy ground v usb0_vssa33 usb0 phy ground v voltage v ih high-level input voltage, dual-voltage i/o, 3.3v (4) 2 v input high high-level input voltage, dual-voltage i/o, 1.8v (4) 0.65*dvdd v high-level input voltage, rtc_xi 0.8*rtc_cvdd v high-level input voltage, oscin 0.8*cvdd v v il low-level input voltage, dual-voltage i/o, 3.3v (4) 0.8 v voltage input low low-level input voltage, dual-voltage i/o, 1.8v (4) 0.35*dvdd v low-level input voltage, rtc_xi 0.2*rtc_cvdd v low-level input voltage, oscin 0.2*cvdd v usb usb0_vbus usb external charge pump input 0 5.25 v transition transition time, 10%-90%, all inputs (unless otherwise t t 0.25p or 10 (5) ns time specified in the electrical data sections) (1) the rtc provides an option for isolating the rtc_cvdd from the cvdd to reduce current leakage when the rtc is powered independently. if these power supplies are not isolated (ctrl.splitpower=0), rtc_cvdd must be equal to or greater than cvdd. if these power supplies are isolated (ctrl.splitpower=1), rtc_cvdd may be lower than cvdd. (2) dvdd18 must be powered even if all of the dvdd3318_x supplies are operated at 3.3v. (3) when an external crystal is used oscillator (osc_vss, rtc_vss) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. these pins are shorted to vss on the device itself and should not be connected to vss on the circuit board. if a crystal is not used and the clock input is driven directly, then the oscillator vss may be connected to board ground. (4) these io specifications apply to the dual-voltage ios only and do not apply to the ddr2/mddr interfaces. ddr2/mddr ios are 1.8v ios and adhere to the jesd79-2a standard. (5) whichever is smaller. where p = the period of the applied signal. maintaining transition times as fast as possible is recommended to improve noise immunity on input signals. 44 specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 recommended operating conditions (continued) name description condition min nom max unit cvdd = 1.2v 0 300 operating point operating industrial temperature grade (d cvdd = 1.1v f pll0_sysclk6 0 200 mhz frequency suffix) operating point cvdd = 1.0v 0 100 operating point copyright ? 2010 ? 2014, texas instruments incorporated specifications 45 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 5.4 notes on recommended power-on hours (poh) the information in the section below is provided solely for your convenience and does not extend or modify the warranty provided under ti ? s standard terms and conditions for ti semiconductor products. to avoid significant degradation, the device power-on hours (poh) must be limited to the following: table 5-1. recommended power-on hours silicon operating junction power-on hours [poh] speed grade nominal cvdd voltage (v) revision temperature (tj) (hours) b/e 300 mhz -40 to 90 c 1.2v 100,000 note: logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. the above notations cannot be deemed a warranty or deemed to extend or modify the warranty under ti ? s standard terms and conditions for ti semiconductor products. 46 specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 5.5 electrical characteristics over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) parameter test conditions min typ max unit dvdd= 3.15v, i oh = -4 ma 2.4 v high-level output voltage (dual-voltage lvcmos ios at 3.3v) (1) dvdd= 3.15v, i oh = -100 a 2.95 v v oh high-level output voltage dvdd= 1.71v, i oh = -2 ma dvdd-0.45 v (dual-voltage lvcmos ios at 1.8v) (1) dvdd= 3.15v, i ol = 4ma 0.4 v low-level output voltage (dual-voltage lvcmos i/os at 3.3v) dvdd= 3.15v, i ol = 100 a 0.2 v v ol low-level output voltage dvdd= 1.71v, i ol = 2ma 0.45 v (dual-voltage lvcmos i/os at 1.8v) v i = vss to dvdd without opposing 9 a internal resistor input current (1) v i = vss to dvdd with opposing 70 310 a (dual-voltage lvcmos i/os) internal pullup resistor (3) i i (2) v i = vss to dvdd with opposing -75 -270 a internal pulldown resistor (3) v i = vss to dvdd with opposing input current (ddr2/mddr i/os) -77 -286 a internal pulldown resistor (3) high-level output current (1) i oh -6 ma (dual-voltage lvcmos i/os) low-level output current (1) i ol 6 ma (dual-voltage lvcmos i/os) input capacitance (dual-voltage 3 pf lvcmos) capacitance output capacitance (dual-voltage 3 pf lvcmos) (1) these io specifications apply to the dual-voltage ios only and do not apply to the ddr2/mddr interface. ddr2/mddr ios are 1.8v ios and adhere to the jesd79-2a standard. usb0 i/os adhere to the usb2.0 standard. (2) i i applies to input-only pins and bi-directional pins. for input-only pins, i i indicates the input leakage current. for bi-directional pins, i i indicates the input leakage current and off-state (hi-z) output leakage current. (3) applies only to pins with an internal pullup (ipu) or pulldown (ipd) resistor. the pull-up and pull-down strengths shown represent the minimum and maximum strength across process variation. copyright ? 2010 ? 2014, texas instruments incorporated specifications 47 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6 peripheral information and electrical specifications 6.1 parameter information 6.1.1 parameter information device-specific information a. the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. a transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin and the input signals are driven between 0v and the appropriate io supply rail for the signal. figure 6-1. test load circuit for ac timing measurements the load capacitance value stated is only for characterization and measurement of ac timing signals. this load capacitance value does not indicate the maximum load the device is capable of driving. 6.1.1.1 signal transition levels all input and output timing parameters are referenced to v ref for both "0" and "1" logic levels. for 3.3 v i/o, v ref = 1.65 v. for 1.8 v i/o, v ref = 0.9 v. for 1.2 v i/o, vref = 0.6 v. figure 6-2. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. figure 6-3. rise and fall transition time voltage reference levels 48 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 v ref = v il max (or v ol max) v ref = v ih min (or v oh min) v ref transmission line 4.0 pf 1.85 pf z0 = 50 (see note) tester pin electronics data sheet timing reference point outputunder test 42 3.5 nh device pin(see note)
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.2 recommended clock and control signal transition behavior all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner. 6.3 power supplies 6.3.1 power-on sequence the device should be powered-on in the following order: 1. rtc (rtc_cvdd) may be powered from an external device (such as a battery) prior to all other supplies being applied or powered-up at the same time as cvdd. if the rtc is not used, rtc_cvdd should be connected to cvdd. rtc_cvdd should not be left unpowered while cvdd is powered. 2. core logic supplies: ( a) all variable 1.2v - 1.0v core logic supplies (cvdd) ( b) all static core logic supplies (rvdd, pll0_vdda, pll1_vdda, usb_cvdd). if voltage scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply and powered up together. 3. all static 1.8v io supplies (dvdd18, ddr_dvdd18, usb0_vdda18) and any of the lvcmos io supply groups used at 1.8v nominal (dvdd3318_a, dvdd3318_b, or dvdd3318_c). 4. all analog 3.3v phy supplies (usb0_vdda33; this is not required if usb0 is not used) and any of the lvcmos io supply groups used at 3.3v nominal (dvdd3318_a, dvdd3318_b, or dvdd3318_c). there is no specific required voltage ramp rate for any of the supplies as long as the lvcmos supplies operated at 3.3v (dvdd3318_a, dvdd3318_b, or dvdd3318_c) never exceed the static 1.8v supplies by more than 2 volts. reset must be maintained active until all power supplies have reached their nominal values. 6.3.2 power-off sequence the power supplies can be powered-off in any order as long as lvcmos supplies operated at 3.3v (dvdd3318_a, dvdd3318_b, or dvdd3318_c) never exceed static 1.8v supplies by more than 2 volts. there is no specific required voltage ramp down rate for any of the supplies (except as required to meet the above mentioned voltage condition). copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 49 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.4 reset 6.4.1 power-on reset (por) a power-on reset (por) is required to place the device in a known good state after power-up. power-on reset is initiated by bringing reset and trst low at the same time. por sets all of the device internal logic to its default state. all pins are tri-stated with the exception of resetout which remains active through the reset sequence, and rtck/gp8[0]. if an emulator is driving tck into the device during reset, then rtck/gp8[0] will drive out rtck. if tck is not being driven into the device during reset, then rtck/gp8[0] will drive low. resetout in an output for use by other controllers in the system that indicates the device is currently in reset. while both trst and reset need to be asserted upon power up, only reset needs to be released for the device to boot properly. trst may be asserted indefinitely for normal operation, keeping the jtag port interface and device's emulation logic in the reset state. trst only needs to be released when it is necessary to use a jtag controller to debug the device or exercise the device's boundary scan functionality. note: trst is synchronous and must be clocked by tck; otherwise, the boundary scan logic may not respond as expected after trst is asserted. reset must be released only in order for boundary-scan jtag to read the variant field of idcode correctly. other boundary-scan instructions work correctly independent of current state of reset. for maximum reliability, the device includes an internal pulldown on the trst pin to ensure that trst will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. jtag controllers from texas instruments actively drive trst high. however, some third-party jtag controllers may not drive trst high but expect the use of a pullup resistor on trst. when using this type of jtag controller, assert trst to intialize the device after powerup and externally drive trst high before attempting any emulation or boundary scan operations. rtck/gp8[0] is maintained active through a por. a summary of the effects of power-on reset is given below: ? all internal logic (including emulation logic and the pll logic) is reset to its default state ? internal memory is not maintained through a por ? resetout goes active ? all device pins go to a high-impedance state ? the rtc peripheral is not reset during a por. a software sequence is required to reset the rtc caution: a watchdog reset triggers a por. 6.4.2 warm reset a warm reset provides a limited reset to the device. warm reset is initiated by bringing only reset low ( trst is maintained high through a warm reset). warm reset sets certain portions of the device to their default state while leaving others unaltered. all pins are tri-stated with the exception of resetout which remains active through the reset sequence, and rtck/gp8[0]. if an emulator is driving tck into the device during reset, then rtck/gp8[0] will drive out rtck. if tck is not being driven into the device during reset, then rtck/gp8[0] will drive low. resetout is an output for use by other controllers in the system that indicates the device is currently in reset. during an emulation, the emulator will maintain trst high and hence only warm reset (not por) is available during emulation debug and development. rtck/gp8[0] is maintained active through a warm reset. a summary of the effects of warm reset is given below: ? all internal logic (except for the emulation logic and the pll logic) is reset to its default state 50 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 ? internal memory is maintained through a warm reset ? resetout goes active ? all device pins go to a high-impedance state ? the rtc peripheral is not reset during a warm reset. a software sequence is required to reset the rtc copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 51 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.4.3 reset electrical data timings table 6-1 assumes testing over the recommended operating conditions. table 6-1. reset timing requirements ( (1) , (2) ) 1.2v 1.1v 1.0v no. unit min max min max min max 1 t w(rstl) pulse width, reset/ trst low 100 100 100 ns 2 t su(bpv-rsth) setup time, boot pins valid before reset/ trst high 20 20 20 ns 3 t h(rsth-bpv) hold time, boot pins valid after reset/ trst high 20 20 20 ns t d(rsth- reset high to resetout high; warm reset 4096 4096 4096 cycles (3) 4 resetouth) reset high to resetout high; power-on reset 6169 6169 6169 t d(rstl- delay time, reset/ trst low to resetout low ns 5 14 16 20 resetoutl) (1) resetout is multiplexed with other pin functions. see the terminal functions table, table 3-3 for details. (2) for power-on reset (por), the reset timings in this table refer to reset and trst together. for warm reset, the reset timings in this table refer to reset only ( trst is held high). (3) oscin cycles. figure 6-4. power-on reset (reset and trst active) timing 52 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 oscin reset resetout boot pins config power supplies ramping power supplies stable clock source stable 1 2 3 4 trst
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-5. warm reset (reset active, trst high) timing copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 53 submit documentation feedback product folder links: am1802 oscin trst reset resetout boot pins config power supplies stable 1 2 3 4 driven or hi-z 5
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.5 crystal oscillator or external clock input the device includes two choices to provide an external clock input, which is fed to the on-chip plls to generate high-frequency system clocks. these options are illustrated in figure 6-6 and figure 6-7 . for input clock frequencies between 12 and 20 mhz, a crystal with 80 ohm max esr is recommended. for input clock frequencies between 20 and 30 mhz, a crystal with 60 ohm max esr is recommended. typical load capacitance values are 10-20 pf, where the load capacitance is the series combination of c1 and c2. the clkmode bit in the pllctl register must be 0 to use the on-chip oscillator. if clkmode is set to 1, the internal oscillator is disabled. figure 6-6 illustrates the option that uses on-chip 1.2v oscillator with external crystal circuit. figure 6-7 illustrates the option that uses an external 1.2v clock input. figure 6-6. on-chip oscillator table 6-2. oscillator timing requirements min max unit f osc oscillator frequency range (oscin/oscout) 12 30 mhz 54 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 c 2 c 1 x 1 oscout oscin oscv ss clock inputto pll
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-7. external 1.2v clock source table 6-3. oscin timing requirements for an externally driven clock min max unit f oscin oscin frequency range 12 50 mhz t c(oscin) cycle time, external clock driven on oscin 20 ns t w(oscinh) pulse width high, external clock on oscin 0.4 t c(oscin) ns t w(oscinl) pulse width low, external clock on oscin 0.4 t c(oscin) ns t t(oscin) transition time, oscin 0.25p or 10 (1) ns t j(oscin) period jitter, oscin 0.02p ns (1) whichever is smaller. p = the period of the applied signal. maintaining transition times as fast as possible is recommended to improve noise immunity on input signals. 6.6 clock plls the device has two pll controllers that provide clocks to different parts of the system. pll0 provides clocks (though various dividers) to most of the components of the device. pll1 provides clocks to the mddr/ddr2 controller and provides an alternate clock source for the async3 clock domain. this allows the peripherals on the async3 clock domain to be immune to frequency scaling operation on pll0. the pll controller provides the following: ? glitch-free transitions (on changing clock settings) ? domain clocks alignment ? clock gating ? pll power down the various clock outputs given by the controller are as follows: ? domain clocks: sysclk [1:n] ? auxiliary clock from reference clock source: auxclk various dividers that can be used are as follows: ? post-pll divider: postdiv ? sysclk divider: d1, ? , dn various other controls supported are as follows: ? pll multiplier control: pllm ? software programmable pll bypass: pllen copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 55 submit documentation feedback product folder links: am1802 oscout oscin oscv ss clockinput to pll nc
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.6.1 pll device-specific information the pll requires some external filtering components to reduce power supply noise as shown in figure 6- 8 . figure 6-8. pll external filtering components the external filtering components shown above provide noise immunity for the plls. pll0_vdda and pll1_vdda should not be connected together to provide noise immunity between the two plls. likewise, pll0_vssa and pll1_vssa should not be connected together. the input to the pll is either from the on-chip oscillator or from an external clock on the oscin pin. pll0 outputs seven clocks that have programmable divider options. pll1 outputs three clocks that have programmable divider options. figure 6-9 illustrates the high-level view of the pll topology. the plls are disabled by default after a device reset. they must be configured by software according to the allowable operating conditions listed in table 6-4 before enabling the device to run from the pll by setting pllen = 1. 56 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 0.1 f 0.01 f 50r 1.14v - 1.32v 50r v ss pll1_vddapll1_vssa ferrite bead: murata blm31pg500sn1l or equivalent 0.1 f 0.01 f 50r 1.14v - 1.32v 50r v ss pll0_vddapll0_vssa
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-9. pll topology copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 57 submit documentation feedback product folder links: am1802 plldiv1 (/1) sysclk1 plldiv2 (/2) sysclk2 plldiv4 (/4) sysclk4 plldiv5 (/3) sysclk5 plldiv6 (/1) sysclk6 plldiv7 (/6) sysclk7 div4.5 1 0 emifa internal clock source cfgchip3[ema_clksrc] 10 prediv pllm 10 square wave crystal pll1_sysclk3 pllctl[extclksrc] auxclk pll plldiv3 (/3) sysclk3 ddr2/mddr internal clock source plldiv2 (/2) plldiv3 (/3) plldiv1 (/1) 01 pllctl[pllen] postdiv pllm pll 01 pllctl[pllen] pllctl[clkmode] postdiv pllc0 obsclk (clkout pin) div4.5 oscdiv pll controller 0 pll controller 1 sysclk2sysclk3 sysclk1 oscin 14h17h 18h 19h 1ah 1bh 1ch 1dh 1eh sysclk1 sysclk2 sysclk3 sysclk4 sysclk5 sysclk6 sysclk7 pllc1 obsclk ocsel[ocsrc] 14h17h 18h 19h sysclk1sysclk2 sysclk3 ocsel[ocsrc] oscdiv pllc1 obsclk deepsleep enable
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-4. allowed pll operating conditions (pll0 and pll1) default no. parameter min max unit value 1 pllrst : assertion time during initialization n/a 1000 n/a ns lock time : the time that the application has to wait for oscin 2 the pll to acquire lock before setting pllen, after n/a n/a cycles changing prediv, pllm, or oscin 3 prediv : pre-divider value /1 /1 /32 30 (if internal oscillator is used) 4 pllref : pll input frequency 12 mhz 50 (if external clock source is used) 5 pllm : pll multiplier values (1) x20 x4 x32 6 pllout : pll output frequency n/a 300 600 mhz 7 postdiv : post-divider value /1 /1 /32 (1) the multiplier values must be chosen such that the pll output frequency (at pllout) is between 300 and 600 mhz, but the frequency going into the sysclk dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given voltage operating point. 6.6.2 device clock generation pll0 is controlled by pll controller 0 and pll1 is controlled by pll controller 1. pllc0 and pllc1 manage the clock ratios, alignment, and gating for the system clocks to the chip. the pllcs are responsible for controlling all modes of the pll through software, in terms of pre-division of the clock inputs (pllc0 only), multiply factors within the plls, and post-division for each of the chip-level clocks from the plls outputs. pllc0 also controls reset propagation through the chip, clock alignment, and test points. pllc0 provides clocks for the majority of the system but pllc1 provides clocks to the mddr/ddr2 controller and the async3 clock domain to provide frequency scaling immunity to a defined set or peripherals. the async3 clock domain can either derive its clock from pll1_sysclk2 (for frequency scaling immunity from pll0) or from pll0_sysclk2 (for synchronous timing with pll0) depending on the application requirements. in addition, some peripherals have specific clock options independent of the async clock domain. 6.6.3 dynamic voltage and frequency scaling (dvfs) the processor supports multiple operating points by scaling voltage and frequency to minimize power consumption for a given level of processor performance. frequency scaling is achieved by modifying the setting of the pll controllers ? multipliers, post-dividers (postdiv), and system clock dividers (sysclkn). modification of the postdiv and sysclk values does not require relocking the pll and provides lower latency to switch between operating points, but at the expense of the frequencies being limited by the integer divide values (only the divide values are altered the pll multiplier is left unmodified). non integer divide frequency values can be achieved by changing both the multiplier and the divide values, but when the pll multiplier is changed the pll must relock, incurring additional latency to change between operating points. detailed information on modifying the pll controller settings can be found in the am1802 arm microprocessor system reference guide (literature number sprugx5 ). voltage scaling is enabled from outside the device by controlling an external voltage regulator. the processor may communicate with the regulator using gpios, i2c or some other interface. when switching between voltage-frequency operating points, the voltage must always support the desired frequency. when moving from a high-performance operating point to a lower performance operating point, the frequency should be lowered first followed by the voltage. when moving from a low-performance operating point to a higher performance operating point, the voltage should be raised first followed by the frequency. voltage operating points refer to the cvdd voltage at that point. other static supplies must be maintained at their nominal voltages at all operating points. 58 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 2000 n max pll lock time = m where n = pre-divider ratio m = pll multiplier
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 the maximum voltage slew rate for cvdd supply changes is 1 mv/us. for additional information on power management solutions from ti for this processor, follow the power management link in the product folder on www.ti.com for this processor. the processor supports multiple clock domains some of which have clock ratio requirements to each other. pll0_sysclk2:pll0_sysclk4:pll0_sysclk6 are synchronous to each other and the sysclkn dividers must always be configured such that the ratio between these domains is 2:4:1. the async and async3 clock domains are asynchronous to the other clock domains and have no specific ratio requirement. the table below summarizes the maximum internal clock frequencies at each of the voltage operating points. table 6-5. maximum internal clock frequencies at each voltage operating point clock source clock domain 1.2v nom 1.1v nom 1.0v nom pll0_sysclk1 not used on this processor - - - sysclk2 clock domain peripherals and optional clock source for async3 pll0_sysclk2 150 mhz 100 mhz 50 mhz clock domain peripherals pll0_sysclk3 optional clock for async1 clock domain pll0_sysclk4 sysclk4 domain peripherals 75 mhz 50 mhz 25 mhz pll0_sysclk5 not used on this processor - - - pll0_sysclk6 arm subsystem 300 mhz 200 mhz 100 mhz pll0_sysclk7 optional 50 mhz clock source for emac rmii interface 50 mhz - - ddr2/mddr interface clock source (memory interface clock is one-half of pll1_sysclk1 312 mhz 300 mhz 266 mhz the value shown) pll1_sysclk2 optional clock source for async3 clock domain peripherals 150 mhz 100 mhz 75 mhz pll1_sysclk3 alternate clock source input to pll controller 0 75 mhz 75 mhz 75 mhz mcasp auxclk bypass clock source for the mcasp 50 mhz 50 mhz 50 mhz pll0_auxclk bypass clock source for the usb0 48 mhz 48 mhz 48 mhz async mode 148 mhz 75 mhz 50 mhz async1 async1 clock domain (emifa) sdram mode 100 mhz 66.6 mhz 50 mhz async2 async2 clock domain (multiple peripherals) 50 mhz 50 mhz 50 mhz some interfaces have specific limitations on supported modes/speeds at each operating point. see the corresponding peripheral sections of this document for more information. ti provides software components (called the power manager) to perform dvfs and abstract the task from the user. the power manager controls changing operating points (both frequency and voltage) and handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions between operating points. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 59 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.7 interrupts 6.7.1 arm cpu interrupts the arm9 cpu core supports 2 direct interrupts: fiq and irq. the arm interrupt controller (aintc) extends the number of interrupts to 100, and provides features like programmable masking, priority, hardware nesting support, and interrupt vector generation. 6.7.1.1 arm interrupt controller (aintc) interrupt signal hierarchy the arm interrupt controller organizes interrupts into the following hierarchy: ? peripheral interrupt requests ? individual interrupt sources from peripherals ? 101 system interrupts ? one or more peripheral interrupt requests are combined (fixed configuration) to generate a system interrupt. ? after prioritization, the aintc will provide an interrupt vector based unique to each system interrupt ? 32 interrupt channels ? each system interrupt is mapped to one of the 32 interrupt channels ? channel number determines the first level of prioritization, channel 0 is highest priority and 31 lowest. ? if more than one system interrupt is mapped to a channel, priority within the channel is determined by system interrupt number (0 highest priority) ? host interrupts (fiq and irq) ? interrupt channels 0 and 1 generate the arm fiq interrupt ? interrupt channels 2 through 31 generate the arm irq interrupt ? debug interrupts ? two debug interrupts are supported and can be used to trigger events in the debug subsystem ? sources can be selected from any of the system interrupts or host interrupts 6.7.1.2 aintc hardware vector generation the aintc also generates an interrupt vector in hardware for both irq and fiq host interrupts. this may be used to accelerate interrupt dispatch. a unique vector is generated for each of the 100 system interrupts. the vector is computed in hardware as: vector = base + (system interrupt number size) where base and size are programmable. the computed vector is a 32-bit address which may dispatched to using a single instruction of type ldr pc, [pc, #- < offset_12 > ] at the fiq and irq vector locations (0xffff0018 and 0xffff001c respectively). 6.7.1.3 aintc hardware interrupt nesting support interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the cpu to interrupt the isr if a higher priority event occurs. the aintc provides hardware support to facilitate interrupt nesting. it supports both global and per host interrupt (fiq and irq in this case) automatic nesting. if enabled, the aintc will automatically update an internal nesting register that temporarily masks interrupts at and below the priority of the current interrupt channel. then if the isr re-enables interrupts; only higher priority channels will be able to interrupt it. the nesting level is restored by the isr by writing to the nesting level register on completion. support for nesting can be enabled/disabled by software, with the option of automatic nesting on a global or per host interrupt basis; or manual nesting. 60 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.7.1.4 aintc system interrupt assignments table 6-6. aintc system interrupt assignments system interrupt interrupt name source 0 commtx arm 1 commrx arm 2 nint arm 3 - reserved 4 - reserved 5 - reserved 6 - reserved 7 - reserved 8 - reserved 9 - reserved 10 - reserved 11 edma3_0_cc0_int0 edma3_0 channel controller 0 shadow region 0 transfer completion interrupt 12 edma3_0_cc0_errint edma3_0 channel controller 0 error interrupt 13 edma3_0_tc0_errint edma3_0 transfer controller 0 error interrupt 14 emifa_int emifa 15 iic0_int i2c0 16 mmcsd0_int0 mmcsd0 mmc/sd interrupt 17 mmcsd0_int1 mmcsd0 sdio interrupt 18 psc0_allint psc0 19 rtc_irqs[1:0] rtc 20 spi0_int spi0 21 t64p0_tint12 timer64p0 interrupt 12 22 t64p0_tint34 timer64p0 interrupt 34 23 t64p1_tint12 timer64p1 interrupt 12 24 t64p1_tint34 timer64p1 interrupt 34 25 uart0_int uart0 26 - reserved 27 mpu_bootcfg_err shared mpu and syscfg address/protection error interrupt 28-31 - reserved 32 edma3_0_tc1_errint edma3_0 transfer controller 1 error interrupt 33 emac_c0rxthresh emac - core 0 receive threshold interrupt 34 emac_c0rx emac - core 0 receive interrupt 35 emac_c0tx emac - core 0 transmit interrupt 36 emac_c0misc emac - core 0 miscellaneous interrupt 37 emac_c1rxthresh emac - core 1 receive threshold interrupt 38 emac_c1rx emac - core 1 receive interrupt 39 emac_c1tx emac - core 1 transmit interrupt 40 emac_c1misc emac - core 1 miscellaneous interrupt 41 ddr2_memerr ddr2 controller 42 gpio_b0int gpio bank 0 interrupt 43 gpio_b1int gpio bank 1 interrupt 44 gpio_b2int gpio bank 2 interrupt 45 gpio_b3int gpio bank 3 interrupt 46 gpio_b4int gpio bank 4 interrupt 47 gpio_b5int gpio bank 5 interrupt copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 61 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-6. aintc system interrupt assignments (continued) system interrupt interrupt name source 48 gpio_b6int gpio bank 6 interrupt 49 gpio_b7int gpio bank 7 interrupt 50 gpio_b8int gpio bank 8 interrupt 51-52 - reserved 53 uart_int1 uart1 54 mcasp_int mcasp0 combined rx / tx interrupts 55 psc1_allint psc1 56 spi1_int spi1 57 - reserved 58 usb0_int usb0 interrupt 59-60 - reserved 61 uart2_int uart2 62-67 - reserved 68 t64p2_all timer64p2 - combined tint12 and tint34 69-73 - reserved 74 t64p2_cmpint0 timer64p2 - compare 0 75 t64p2_cmpint1 timer64p2 - compare 1 76 t64p2_cmpint2 timer64p2 - compare 2 77 t64p2_cmpint3 timer64p2 - compare 3 78 t64p2_cmpint4 timer64p2 - compare 4 79 t64p2_cmpint5 timer64p2 - compare 5 80 t64p2_cmpint6 timer64p2 - compare 6 81 t64p2_cmpint7 timer64p2 - compare 7 82 t64p3_cmpint0 timer64p3 - compare 0 83 t64p3_cmpint1 timer64p3 - compare 1 84 t64p3_cmpint2 timer64p3 - compare 2 85 t64p3_cmpint3 timer64p3 - compare 3 86 t64p3_cmpint4 timer64p3 - compare 4 87 t64p3_cmpint5 timer64p3 - compare 5 88 t64p3_cmpint6 timer64p3 - compare 6 89 t64p3_cmpint7 timer64p3 - compare 7 90 armclkstopreq psc0 91-92 - reserved 93 edma3_1_cc0_int0 edma3_1 channel controller 0 shadow region 0 transfer completion interrupt 94 edma3_1_cc0_errint edma3_1channel controller 0 error interrupt 95 edma3_1_tc0_errint edma3_1 transfer controller 0 error interrupt 96 t64p3_all timer64p 3 - combined tint12 and tint34 97-100 - reserved 62 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.7.1.5 aintc memory map table 6-7. aintc memory map byte address acronym description 0xfffe e000 rev revision register 0xfffe e004 cr control register 0xfffe e008 - 0xfffe e00f - reserved 0xfffe e010 ger global enable register 0xfffe e014 - 0xfffe e01b - reserved 0xfffe e01c gnlr global nesting level register 0xfffe e020 sisr system interrupt status indexed set register 0xfffe e024 sicr system interrupt status indexed clear register 0xfffe e028 eisr system interrupt enable indexed set register 0xfffe e02c eicr system interrupt enable indexed clear register 0xfffe e030 - reserved 0xfffe e034 hieisr host interrupt enable indexed set register 0xfffe e038 hidisr host interrupt enable indexed clear register 0xfffe e03c - 0xfffe e04f - reserved 0xfffe e050 vbr vector base register 0xfffe e054 vsr vector size register 0xfffe e058 vnr vector null register 0xfffe e05c - 0xfffe e07f - reserved 0xfffe e080 gpir global prioritized index register 0xfffe e084 gpvr global prioritized vector register 0xfffe e088 - 0xfffe e1ff - reserved 0xfffe e200 srsr[0] system interrupt status raw / set registers 0xfffe e204 srsr[1] 0xfffe e208 srsr[2] 0xfffe e20c srsr[3] 0xfffe e210- 0xfffe e27f - reserved 0xfffe e280 secr[0] system interrupt status enabled / clear registers 0xfffe e284 secr[1] 0xfffe e288 secr[2] 0xfffe e28c secr[3] 0xfffe e290 - 0xfffe e2ff - reserved 0xfffe e300 esr[0] system interrupt enable set registers 0xfffe e304 esr[1] 0xfffe e308 esr[2] 0xfffe e30c esr[3] 0xfffe e310 - 0xfffe e37f - reserved 0xfffe e380 ecr[0] system interrupt enable clear registers 0xfffe e384 ecr[1] 0xfffe e388 ecr[2] 0xfffe e38c ecr[3] 0xfffe e390 - 0xfffe e3ff - reserved copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 63 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-7. aintc memory map (continued) byte address acronym description 0xfffe e400 - 0xfffe e45b cmr[0] channel map registers 0xfffe e404 cmr[1] 0xfffe e408 cmr[2] 0xfffe e40c cmr[3] 0xfffe e410 cmr[4] 0xfffe e414 cmr[5] 0xfffe e418 cmr[6] 0xfffe e41c cmr[7] 0xfffe e420 cmr[8] 0xfffe e424 cmr[9] 0xfffe e428 cmr[10] 0xfffe e42c cmr[11] 0xfffe e430 cmr[12] 0xfffe e434 cmr[13] 0xfffe e438 cmr[14] 0xfffe e43c cmr[15] 0xfffe e440 cmr[16] 0xfffe e444 cmr[17] 0xfffe e448 cmr[18] 0xfffe e44c cmr[19] 0xfffe e450 cmr[20] 0xfffe e454 cmr[21] 0xfffe e458 cmr[22] 0xfffe e45c cmr[23] 0xfffe e460 cmr[24] 0xfffe e464 cmr[25] 0xfffe e468 - 0xfffe e8ff - reserved 0xfffe e900 hipir[0] host interrupt prioritized index registers 0xfffe e904 hipir[1] 0xfffe e908 - 0xfffe eeff - reserved 0xfffe ef00 dsr[0] debug select registers 0xfffe ef04 dsr[1] 0xfffe ef08 - 0xfffe f0ff - reserved 0xfffe f100 hinlr[0] host interrupt nesting level registers 0xfffe f104 hinlr[1] 0xfffe f108 - 0xfffe f4ff - reserved 0xfffe f500 hier[0] host interrupt enable register 0xfffe f504 - 0xfffe f5ff - reserved 0xfffe f600 hipvr[0] - host interrupt prioritized vector registers 0xfffe f604 hipvr[1] 0xfffe f608 - 0xfffe ffff - reserved 64 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.8 power and sleep controller (psc) the power and sleep controllers (psc) are responsible for managing transitions of system power on/off, clock on/off, resets (device level and module level). it is used primarily to provide granular power control for on chip modules (peripherals and cpu). a psc module consists of a global psc (gpsc) and a set of local pscs (lpscs). the gpsc contains memory mapped registers, psc interrupts, a state machine for each peripheral/module it controls. an lpsc is associated with every module that is controlled by the psc and provides clock and reset control. the psc includes the following features: ? provides a software interface to: ? control module clock enable/disable ? control module reset ? control cpu local reset ? supports icepick emulation features: power, clock and reset psc0 controls 16 local pscs. psc1 controls 32 local pscs. table 6-8. power and sleep controller (psc) registers psc0 byte psc1 byte acronym register description address address 0x01c1 0000 0x01e2 7000 revid peripheral revision and class information register 0x01c1 0018 0x01e2 7018 inteval interrupt evaluation register 0x01c1 0040 0x01e2 7040 merrpr0 module error pending register 0 (module 0-15) (psc0) module error pending register 0 (module 0-31) (psc1) 0x01c1 0050 0x01e2 7050 merrcr0 module error clear register 0 (module 0-15) (psc0) module error clear register 0 (module 0-31) (psc1) 0x01c1 0060 0x01e2 7060 perrpr power error pending register 0x01c1 0068 0x01e2 7068 perrcr power error clear register 0x01c1 0120 0x01e2 7120 ptcmd power domain transition command register 0x01c1 0128 0x01e2 7128 ptstat power domain transition status register 0x01c1 0200 0x01e2 7200 pdstat0 power domain 0 status register 0x01c1 0204 0x01e2 7204 pdstat1 power domain 1 status register 0x01c1 0300 0x01e2 7300 pdctl0 power domain 0 control register 0x01c1 0304 0x01e2 7304 pdctl1 power domain 1 control register 0x01c1 0400 0x01e2 7400 pdcfg0 power domain 0 configuration register 0x01c1 0404 0x01e2 7404 pdcfg1 power domain 1 configuration register 0x01c1 0800 0x01e2 7800 mdstat0 module 0 status register 0x01c1 0804 0x01e2 7804 mdstat1 module 1 status register 0x01c1 0808 0x01e2 7808 mdstat2 module 2 status register 0x01c1 080c 0x01e2 780c mdstat3 module 3 status register 0x01c1 0810 0x01e2 7810 mdstat4 module 4 status register 0x01c1 0814 0x01e2 7814 mdstat5 module 5 status register 0x01c1 0818 0x01e2 7818 mdstat6 module 6 status register 0x01c1 081c 0x01e2 781c mdstat7 module 7 status register 0x01c1 0820 0x01e2 7820 mdstat8 module 8 status register 0x01c1 0824 0x01e2 7824 mdstat9 module 9 status register 0x01c1 0828 0x01e2 7828 mdstat10 module 10 status register 0x01c1 082c 0x01e2 782c mdstat11 module 11 status register 0x01c1 0830 0x01e2 7830 mdstat12 module 12 status register 0x01c1 0834 0x01e2 7834 mdstat13 module 13 status register copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 65 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-8. power and sleep controller (psc) registers (continued) psc0 byte psc1 byte acronym register description address address 0x01c1 0838 0x01e2 7838 mdstat14 module 14 status register 0x01c1 083c 0x01e2 783c mdstat15 module 15 status register - 0x01e2 7840 mdstat16 module 16 status register - 0x01e2 7844 mdstat17 module 17 status register - 0x01e2 7848 mdstat18 module 18 status register - 0x01e2 784c mdstat19 module 19 status register - 0x01e2 7850 mdstat20 module 20 status register - 0x01e2 7854 mdstat21 module 21 status register - 0x01e2 7858 mdstat22 module 22 status register - 0x01e2 785c mdstat23 module 23 status register - 0x01e2 7860 mdstat24 module 24 status register - 0x01e2 7864 mdstat25 module 25 status register - 0x01e2 7868 mdstat26 module 26 status register - 0x01e2 786c mdstat27 module 27 status register - 0x01e2 7870 mdstat28 module 28 status register - 0x01e2 7874 mdstat29 module 29 status register - 0x01e2 7878 mdstat30 module 30 status register - 0x01e2 787c mdstat31 module 31 status register 0x01c1 0a00 0x01e2 7a00 mdctl0 module 0 control register 0x01c1 0a04 0x01e2 7a04 mdctl1 module 1 control register 0x01c1 0a08 0x01e2 7a08 mdctl2 module 2 control register 0x01c1 0a0c 0x01e2 7a0c mdctl3 module 3 control register 0x01c1 0a10 0x01e2 7a10 mdctl4 module 4 control register 0x01c1 0a14 0x01e2 7a14 mdctl5 module 5 control register 0x01c1 0a18 0x01e2 7a18 mdctl6 module 6 control register 0x01c1 0a1c 0x01e2 7a1c mdctl7 module 7 control register 0x01c1 0a20 0x01e2 7a20 mdctl8 module 8 control register 0x01c1 0a24 0x01e2 7a24 mdctl9 module 9 control register 0x01c1 0a28 0x01e2 7a28 mdctl10 module 10 control register 0x01c1 0a2c 0x01e2 7a2c mdctl11 module 11 control register 0x01c1 0a30 0x01e2 7a30 mdctl12 module 12 control register 0x01c1 0a34 0x01e2 7a34 mdctl13 module 13 control register 0x01c1 0a38 0x01e2 7a38 mdctl14 module 14 control register 0x01c1 0a3c 0x01e2 7a3c mdctl15 module 15 control register - 0x01e2 7a40 mdctl16 module 16 control register - 0x01e2 7a44 mdctl17 module 17 control register - 0x01e2 7a48 mdctl18 module 18 control register - 0x01e2 7a4c mdctl19 module 19 control register - 0x01e2 7a50 mdctl20 module 20 control register - 0x01e2 7a54 mdctl21 module 21 control register - 0x01e2 7a58 mdctl22 module 22 control register - 0x01e2 7a5c mdctl23 module 23 control register - 0x01e2 7a60 mdctl24 module 24 control register - 0x01e2 7a64 mdctl25 module 25 control register - 0x01e2 7a68 mdctl26 module 26 control register - 0x01e2 7a6c mdctl27 module 27 control register - 0x01e2 7a70 mdctl28 module 28 control register 66 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-8. power and sleep controller (psc) registers (continued) psc0 byte psc1 byte acronym register description address address - 0x01e2 7a74 mdctl29 module 29 control register - 0x01e2 7a78 mdctl30 module 30 control register - 0x01e2 7a7c mdctl31 module 31 control register 6.8.1 power domain and module topology the device includes two psc modules. each psc module controls clock states for several of the on chip modules, controllers and interconnect components. table 6-9 and table 6-10 lists the set of peripherals/modules that are controlled by the psc, the power domain they are associated with, the lpsc assignment and the default (power-on reset) module states. see the device-specific data manual for the peripherals available on a given device. the module states and terminology are defined in section 6.8.1.1 . table 6-9. psc0 default module configuration lpsc module name power domain default module state auto sleep/wake only number 0 edma3 channel controller 0 alwayson (pd0) swrstdisable ? 1 edma3 transfer controller 0 alwayson (pd0) swrstdisable ? 2 edma3 transfer controller 1 alwayson (pd0) swrstdisable ? 3 emifa (br7) alwayson (pd0) swrstdisable ? 4 spi 0 alwayson (pd0) swrstdisable ? 5 mmc/sd 0 alwayson (pd0) swrstdisable ? 6 arm interrupt controller alwayson (pd0) swrstdisable ? 7 arm ram/rom alwayson (pd0) enable yes 8 ? ? ? ? 9 uart 0 alwayson (pd0) swrstdisable ? 10 scr0 (br 0, br 1, br 2, br 8) alwayson (pd0) enable yes 11 scr1 (br 4) alwayson (pd0) enable yes 12 scr2 (br 3, br 5, br 6) alwayson (pd0) enable yes 13 ? ? ? ? 14 arm alwayson (pd0) swrstdisable ? 15 ? ? ? ? copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 67 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-10. psc1 default module configuration lpsc module name power domain default module state auto sleep/wake only number 0 edma3 channel controller 1 alwayson (pd0) swrstdisable ? 1 usb0 (usb2.0) alwayson (pd0) swrstdisable ? 2 ? ? ? ? 3 gpio alwayson (pd0) swrstdisable ? 4 ? alwayson (pd0) swrstdisable ? 5 emac alwayson (pd0) swrstdisable ? 6 ddr2 (and scr_f3) alwayson (pd0) swrstdisable ? 7 mcasp0 ( + mcasp0 fifo) alwayson (pd0) swrstdisable ? 8-9 ? ? ? ? 10 spi 1 alwayson (pd0) swrstdisable ? 11 ? ? ? ? 12 uart 1 alwayson (pd0) swrstdisable ? 13 uart 2 alwayson (pd0) swrstdisable ? 14-20 ? ? ? ? 21 edma3 transfer controller 2 alwayson (pd0) swrstdisable ? 22-23 ? ? ? ? 24 scr_f0 (and bridge f0) alwayson (pd0) enable yes 25 scr_f1 (and bridge f1) alwayson (pd0) enable yes 26 scr_f2 (and bridge f2) alwayson (pd0) enable yes 27 scr_f6 (and bridge f3) alwayson (pd0) enable yes 28 scr_f7 (and bridge f4) alwayson (pd0) enable yes 29 scr_f8 (and bridge f5) alwayson (pd0) enable yes 30 bridge f7 (ddr controller alwayson (pd0) enable yes path) 31 on-chip ram (including pd_shram enable ? scr_f4 and bridge f6) 68 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.8.1.1 module states the psc defines several possible states for a module. this states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled. the module states are defined in table 6-11 . table 6-11. module states module state module reset module module state definition clock enable de-asserted on a module in the enable state has its module reset de-asserted and it has its clock on. this is the normal operational state for a given module disable de-asserted off a module in the disabled state has its module reset de-asserted and it has its module clock off. this state is typically used for disabling a module clock to save power. the device is designed in full static cmos, so when you stop a module clock, it retains the module ? s state. when the clock is restarted, the module resumes operating from the stopping point. syncreset asserted on a module state in the syncreset state has its module reset asserted and it has its clock on. generally, software is not expected to initiate this state swrstdisable asserted off a module in the swresetdisable state has its module reset asserted and it has its clock disabled. after initial power-on, several modules come up in the swrstdisable state. generally, software is not expected to initiate this state auto sleep de-asserted off a module in the auto sleep state also has its module reset de-asserted and its module clock disabled, similar to the disable state. however this is a special state, once a module is configured in this state by software, it can ? automatically ? transition to ? enable ? state whenever there is an internal read/write request made to it, and after servicing the request it will ? automatically ? transition into the sleep state (with module reset re de-asserted and module clock disabled), without any software intervention. the transition from sleep to enabled and back to sleep state has some cycle latency associated with it. it is not envisioned to use this mode when peripherals are fully operational and moving data. auto wake de-asserted off a module in the auto wake state also has its module reset de-asserted and its module clock disabled, similar to the disable state. however this is a special state, once a module is configured in this state by software, it will ? automatically ? transition to ? enable ? state whenever there is an internal read/write request made to it, and will remain in the ? enabled ? state from then on (with module reset re de-asserted and module clock on), without any software intervention. the transition from sleep to enabled state has some cycle latency associated with it. it is not envisioned to use this mode when peripherals are fully operational and moving data. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 69 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.9 edma the edma controller handles all data transfers between memories and the device slave peripherals on the device. these data transfers include cache servicing, non-cacheable memory accesses, user- programmed data transfers, and host accesses. 6.9.1 edma3 channel synchronization events each edma channel controller supports up to 32 channels which service peripherals and memory. table 6-12 lists the source of the edma synchronization events associated with each of the programmable edma channels. table 6-12. edma synchronization events edma0 channel controller 0 event event name / source event event name / source 0 mcasp0 receive 16 mmcsd0 receive 1 mcasp0 transmit 17 mmcsd0 transmit 2 reserved 18 spi1 receive 3 reserved 19 spi1 transmit 4 reserved 20 reserved 5 reserved 21 reserved 6 gpio bank 0 interrupt 22 gpio bank 2 interrupt 7 gpio bank 1 interrupt 23 gpio bank 3 interrupt 8 uart0 receive 24 i2c0 receive 9 uart0 transmit 25 i2c0 transmit 10 timer64p0 event out 12 26 reserved 11 timer64p0 event out 34 27 reserved 12 uart1 receive 28 gpio bank 4 interrupt 13 uart1 transmit 29 gpio bank 5 interrupt 14 spi0 receive 30 uart2 receive 15 spi0 transmit 31 uart2 transmit edma1 channel controller 1 event event name / source event event name / source 0 timer64p2 compare event 0 16 gpio bank 6 interrupt 1 timer64p2 compare event 1 17 gpio bank 7 interrupt 2 timer64p2 compare event 2 18 gpio bank 8 interrupt 3 timer64p2 compare event 3 19 reserved 4 timer64p2 compare event 4 20 reserved 5 timer64p2 compare event 5 21 reserved 6 timer64p2 compare event 6 22 reserved 7 timer64p2 compare event 7 23 reserved 8 timer64p3 compare event 0 24 timer64p2 event out 12 9 timer64p3 compare event 1 25 timer64p2 event out 34 10 timer64p3 compare event 2 26 timer64p3 event out 12 11 timer64p3 compare event 3 27 timer64p3 event out 34 12 timer64p3 compare event 4 28 reserved 13 timer64p3 compare event 5 29 reserved 14 timer64p3 compare event 6 30 reserved 15 timer64p3 compare event 7 31 reserved 70 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.9.2 edma peripheral register descriptions table 6-13 is the list of edma3 channel controller registers and table 6-14 is the list of edma3 transfer controller registers. table 6-13. edma3 channel controller (edma3cc) registers edma0 channel controller 0 edma1 channel controller 0 acronym register description byte address byte address 0x01c0 0000 0x01e3 0000 pid peripheral identification register 0x01c0 0004 0x01e3 0004 cccfg edma3cc configuration register global registers 0x01c0 0200 0x01e3 0200 qchmap0 qdma channel 0 mapping register 0x01c0 0204 0x01e3 0204 qchmap1 qdma channel 1 mapping register 0x01c0 0208 0x01e3 0208 qchmap2 qdma channel 2 mapping register 0x01c0 020c 0x01e3 020c qchmap3 qdma channel 3 mapping register 0x01c0 0210 0x01e3 0210 qchmap4 qdma channel 4 mapping register 0x01c0 0214 0x01e3 0214 qchmap5 qdma channel 5 mapping register 0x01c0 0218 0x01e3 0218 qchmap6 qdma channel 6 mapping register 0x01c0 021c 0x01e3 021c qchmap7 qdma channel 7 mapping register 0x01c0 0240 0x01e3 0240 dmaqnum0 dma channel queue number register 0 0x01c0 0244 0x01e3 0244 dmaqnum1 dma channel queue number register 1 0x01c0 0248 0x01e3 0248 dmaqnum2 dma channel queue number register 2 0x01c0 024c 0x01e3 024c dmaqnum3 dma channel queue number register 3 0x01c0 0260 0x01e3 0260 qdmaqnum qdma channel queue number register 0x01c0 0284 0x01e3 0284 quepri queue priority register (1) 0x01c0 0300 0x01e3 0300 emr event missed register 0x01c0 0308 0x01e3 0308 emcr event missed clear register 0x01c0 0310 0x01e3 0310 qemr qdma event missed register 0x01c0 0314 0x01e3 0314 qemcr qdma event missed clear register 0x01c0 0318 0x01e3 0318 ccerr edma3cc error register 0x01c0 031c 0x01e3 031c ccerrclr edma3cc error clear register 0x01c0 0320 0x01e3 0320 eeval error evaluate register 0x01c0 0340 0x01e3 0340 drae0 dma region access enable register for region 0 0x01c0 0348 0x01e3 0348 drae1 dma region access enable register for region 1 0x01c0 0350 0x01e3 0350 drae2 dma region access enable register for region 2 0x01c0 0358 0x01e3 0358 drae3 dma region access enable register for region 3 0x01c0 0380 0x01e3 0380 qrae0 qdma region access enable register for region 0 0x01c0 0384 0x01e3 0384 qrae1 qdma region access enable register for region 1 0x01c0 0388 0x01e3 0388 qrae2 qdma region access enable register for region 2 0x01c0 038c 0x01e3 038c qrae3 qdma region access enable register for region 3 0x01c0 0400 - 0x01c0 043c 0x01e3 0400 - 0x01e3 043c q0e0-q0e15 event queue entry registers q0e0-q0e15 0x01c0 0440 - 0x01c0 047c 0x01e3 0440 - 0x01e3 047c q1e0-q1e15 event queue entry registers q1e0-q1e15 0x01c0 0600 0x01e3 0600 qstat0 queue 0 status register 0x01c0 0604 0x01e3 0604 qstat1 queue 1 status register 0x01c0 0620 0x01e3 0620 qwmthra queue watermark threshold a register 0x01c0 0640 0x01e3 0640 ccstat edma3cc status register global channel registers 0x01c0 1000 0x01e3 1000 er event register (1) on previous architectures, the edma3tc priority was controlled by the queue priority register (quepri) in the edma3cc memory- map. however for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the system configuration module. you should use the chip-level registers and not quepri to configure the tc priority. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 71 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-13. edma3 channel controller (edma3cc) registers (continued) edma0 channel controller 0 edma1 channel controller 0 acronym register description byte address byte address 0x01c0 1008 0x01e3 1008 ecr event clear register 0x01c0 1010 0x01e3 1010 esr event set register 0x01c0 1018 0x01e3 1018 cer chained event register 0x01c0 1020 0x01e3 1020 eer event enable register 0x01c0 1028 0x01e3 1028 eecr event enable clear register 0x01c0 1030 0x01e3 1030 eesr event enable set register 0x01c0 1038 0x01e3 1038 ser secondary event register 0x01c0 1040 0x01e3 1040 secr secondary event clear register 0x01c0 1050 0x01e3 1050 ier interrupt enable register 0x01c0 1058 0x01e3 1058 iecr interrupt enable clear register 0x01c0 1060 0x01e3 1060 iesr interrupt enable set register 0x01c0 1068 0x01e3 1068 ipr interrupt pending register 0x01c0 1070 0x01e3 1070 icr interrupt clear register 0x01c0 1078 0x01e3 1078 ieval interrupt evaluate register 0x01c0 1080 0x01e3 1080 qer qdma event register 0x01c0 1084 0x01e3 1084 qeer qdma event enable register 0x01c0 1088 0x01e3 1088 qeecr qdma event enable clear register 0x01c0 108c 0x01e3 108c qeesr qdma event enable set register 0x01c0 1090 0x01e3 1090 qser qdma secondary event register 0x01c0 1094 0x01e3 1094 qsecr qdma secondary event clear register shadow region 0 channel registers 0x01c0 2000 0x01e3 2000 er event register 0x01c0 2008 0x01e3 2008 ecr event clear register 0x01c0 2010 0x01e3 2010 esr event set register 0x01c0 2018 0x01e3 2018 cer chained event register 0x01c0 2020 0x01e3 2020 eer event enable register 0x01c0 2028 0x01e3 2028 eecr event enable clear register 0x01c0 2030 0x01e3 2030 eesr event enable set register 0x01c0 2038 0x01e3 2038 ser secondary event register 0x01c0 2040 0x01e3 2040 secr secondary event clear register 0x01c0 2050 0x01e3 2050 ier interrupt enable register 0x01c0 2058 0x01e3 2058 iecr interrupt enable clear register 0x01c0 2060 0x01e3 2060 iesr interrupt enable set register 0x01c0 2068 0x01e3 2068 ipr interrupt pending register 0x01c0 2070 0x01e3 2070 icr interrupt clear register 0x01c0 2078 0x01e3 2078 ieval interrupt evaluate register 0x01c0 2080 0x01e3 2080 qer qdma event register 0x01c0 2084 0x01e3 2084 qeer qdma event enable register 0x01c0 2088 0x01e3 2088 qeecr qdma event enable clear register 0x01c0 208c 0x01e3 208c qeesr qdma event enable set register 0x01c0 2090 0x01e3 2090 qser qdma secondary event register 0x01c0 2094 0x01e3 2094 qsecr qdma secondary event clear register shadow region 1 channel registers 0x01c0 2200 0x01e3 2200 er event register 0x01c0 2208 0x01e3 2208 ecr event clear register 0x01c0 2210 0x01e3 2210 esr event set register 0x01c0 2218 0x01e3 2218 cer chained event register 72 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-13. edma3 channel controller (edma3cc) registers (continued) edma0 channel controller 0 edma1 channel controller 0 acronym register description byte address byte address 0x01c0 2220 0x01e3 2220 eer event enable register 0x01c0 2228 0x01e3 2228 eecr event enable clear register 0x01c0 2230 0x01e3 2230 eesr event enable set register 0x01c0 2238 0x01e3 2238 ser secondary event register 0x01c0 2240 0x01e3 2240 secr secondary event clear register 0x01c0 2250 0x01e3 2250 ier interrupt enable register 0x01c0 2258 0x01e3 2258 iecr interrupt enable clear register 0x01c0 2260 0x01e3 2260 iesr interrupt enable set register 0x01c0 2268 0x01e3 2268 ipr interrupt pending register 0x01c0 2270 0x01e3 2270 icr interrupt clear register 0x01c0 2278 0x01e3 2278 ieval interrupt evaluate register 0x01c0 2280 0x01e3 2280 qer qdma event register 0x01c0 2284 0x01e3 2284 qeer qdma event enable register 0x01c0 2288 0x01e3 2288 qeecr qdma event enable clear register 0x01c0 228c 0x01e3 228c qeesr qdma event enable set register 0x01c0 2290 0x01e3 2290 qser qdma secondary event register 0x01c0 2294 0x01e3 2294 qsecr qdma secondary event clear register 0x01c0 4000 - 0x01c0 4fff 0x01e3 4000 - 0x01e3 4fff ? parameter ram (param) table 6-14. edma3 transfer controller (edma3tc) registers edma0 edma0 edma1 acronym register description transfer controller transfer controller transfer controller 0 1 0 byte address byte address byte address 0x01c0 8000 0x01c0 8400 0x01e3 8000 pid peripheral identification register 0x01c0 8004 0x01c0 8404 0x01e3 8004 tccfg edma3tc configuration register 0x01c0 8100 0x01c0 8500 0x01e3 8100 tcstat edma3tc channel status register 0x01c0 8120 0x01c0 8520 0x01e3 8120 errstat error status register 0x01c0 8124 0x01c0 8524 0x01e3 8124 erren error enable register 0x01c0 8128 0x01c0 8528 0x01e3 8128 errclr error clear register 0x01c0 812c 0x01c0 852c 0x01e3 812c errdet error details register 0x01c0 8130 0x01c0 8530 0x01e3 8130 errcmd error interrupt command register 0x01c0 8140 0x01c0 8540 0x01e3 8140 rdrate read command rate register 0x01c0 8240 0x01c0 8640 0x01e3 8240 saopt source active options register 0x01c0 8244 0x01c0 8644 0x01e3 8244 sasrc source active source address register 0x01c0 8248 0x01c0 8648 0x01e3 8248 sacnt source active count register 0x01c0 824c 0x01c0 864c 0x01e3 824c sadst source active destination address register 0x01c0 8250 0x01c0 8650 0x01e3 8250 sabidx source active b-index register 0x01c0 8254 0x01c0 8654 0x01e3 8254 sampprxy source active memory protection proxy register 0x01c0 8258 0x01c0 8658 0x01e3 8258 sacntrld source active count reload register 0x01c0 825c 0x01c0 865c 0x01e3 825c sasrcbref source active source address b-reference register 0x01c0 8260 0x01c0 8660 0x01e3 8260 sadstbref source active destination address b-reference register 0x01c0 8280 0x01c0 8680 0x01e3 8280 dfcntrld destination fifo set count reload register 0x01c0 8284 0x01c0 8684 0x01e3 8284 dfsrcbref destination fifo set source address b-reference register 0x01c0 8288 0x01c0 8688 0x01e3 8288 dfdstbref destination fifo set destination address b- reference register copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 73 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-14. edma3 transfer controller (edma3tc) registers (continued) edma0 edma0 edma1 acronym register description transfer controller transfer controller transfer controller 0 1 0 byte address byte address byte address 0x01c0 8300 0x01c0 8700 0x01e3 8300 dfopt0 destination fifo options register 0 0x01c0 8304 0x01c0 8704 0x01e3 8304 dfsrc0 destination fifo source address register 0 0x01c0 8308 0x01c0 8708 0x01e3 8308 dfcnt0 destination fifo count register 0 0x01c0 830c 0x01c0 870c 0x01e3 830c dfdst0 destination fifo destination address register 0 0x01c0 8310 0x01c0 8710 0x01e3 8310 dfbidx0 destination fifo b-index register 0 0x01c0 8314 0x01c0 8714 0x01e3 8314 dfmpprxy0 destination fifo memory protection proxy register 0 0x01c0 8340 0x01c0 8740 0x01e3 8340 dfopt1 destination fifo options register 1 0x01c0 8344 0x01c0 8744 0x01e3 8344 dfsrc1 destination fifo source address register 1 0x01c0 8348 0x01c0 8748 0x01e3 8348 dfcnt1 destination fifo count register 1 0x01c0 834c 0x01c0 874c 0x01e3 834c dfdst1 destination fifo destination address register 1 0x01c0 8350 0x01c0 8750 0x01e3 8350 dfbidx1 destination fifo b-index register 1 0x01c0 8354 0x01c0 8754 0x01e3 8354 dfmpprxy1 destination fifo memory protection proxy register 1 0x01c0 8380 0x01c0 8780 0x01e3 8380 dfopt2 destination fifo options register 2 0x01c0 8384 0x01c0 8784 0x01e3 8384 dfsrc2 destination fifo source address register 2 0x01c0 8388 0x01c0 8788 0x01e3 8388 dfcnt2 destination fifo count register 2 0x01c0 838c 0x01c0 878c 0x01e3 838c dfdst2 destination fifo destination address register 2 0x01c0 8390 0x01c0 8790 0x01e3 8390 dfbidx2 destination fifo b-index register 2 0x01c0 8394 0x01c0 8794 0x01e3 8394 dfmpprxy2 destination fifo memory protection proxy register 2 0x01c0 83c0 0x01c0 87c0 0x01e3 83c0 dfopt3 destination fifo options register 3 0x01c0 83c4 0x01c0 87c4 0x01e3 83c4 dfsrc3 destination fifo source address register 3 0x01c0 83c8 0x01c0 87c8 0x01e3 83c8 dfcnt3 destination fifo count register 3 0x01c0 83cc 0x01c0 87cc 0x01e3 83cc dfdst3 destination fifo destination address register 3 0x01c0 83d0 0x01c0 87d0 0x01e3 83d0 dfbidx3 destination fifo b-index register 3 0x01c0 83d4 0x01c0 87d4 0x01e3 83d4 dfmpprxy3 destination fifo memory protection proxy register 3 table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128 edma events. each of the parameter register sets consist of 8 32-bit word entries. table 6-16 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. table 6-15. edma parameter set ram edma0 edma1 channel controller 0 channel controller 0 description byte address range byte address range 0x01c0 4000 - 0x01c0 401f 0x01e3 4000 - 0x01e3 401f parameters set 0 (8 32-bit words) 0x01c0 4020 - 0x01c0 403f 0x01e3 4020 - 0x01e3 403f parameters set 1 (8 32-bit words) 0x01c0 4040 - 0x01cc0 405f 0x01e3 4040 - 0x01ce3 405f parameters set 2 (8 32-bit words) 0x01c0 4060 - 0x01c0 407f 0x01e3 4060 - 0x01e3 407f parameters set 3 (8 32-bit words) 0x01c0 4080 - 0x01c0 409f 0x01e3 4080 - 0x01e3 409f parameters set 4 (8 32-bit words) 0x01c0 40a0 - 0x01c0 40bf 0x01e3 40a0 - 0x01e3 40bf parameters set 5 (8 32-bit words) ... ... ... 0x01c0 4fc0 - 0x01c0 4fdf 0x01e3 4fc0 - 0x01e3 4fdf parameters set 126 (8 32-bit words) 0x01c0 4fe0 - 0x01c0 4fff 0x01e3 4fe0 - 0x01e3 4fff parameters set 127 (8 32-bit words) 74 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-16. parameter set entries offset byte address acronym parameter entry within the parameter set 0x0000 opt option 0x0004 src source address 0x0008 a_b_cnt a count, b count 0x000c dst destination address 0x0010 src_dst_bidx source b index, destination b index 0x0014 link_bcntrld link address, b count reload 0x0018 src_dst_cidx source c index, destination c index 0x001c ccnt c count copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 75 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.10 external memory interface a (emifa) emifa is one of two external memory interfaces supported on the device. it is primarily intended to support asynchronous memory types, such as nand and nor flash and asynchronous sram. however on this device, emifa also provides a secondary interface to sdram. 6.10.1 emifa asynchronous memory support emifa supports asynchronous: ? sram memories ? nand flash memories ? nor flash memories the emifa data bus width is up to 16-bits.the device supports up to 23 address lines and two external wait/interrupt inputs. up to four asynchronous chip selects are supported by emifa (ema_cs[5:2]). each chip select has the following individually programmable attributes: ? data bus width ? read cycle timings: setup, hold, strobe ? write cycle timings: setup, hold, strobe ? bus turn around time ? extended wait option with programmable timeout ? select strobe option ? nand flash controller supports 1-bit and 4-bit ecc calculation on blocks of 512 bytes. 6.10.2 emifa synchronous dram memory support the device supports 16-bit sdram in addition to the asynchronous memories listed in section 6.10.1 . it has a single sdram chip select (ema_cs[0]). sdram configurations that are supported are: ? one, two, and four bank sdram devices ? devices with eight, nine, ten, and eleven column address ? cas latency of two or three clock cycles ? sixteen bit data bus width additionally, the sdram interface of emifa supports placing the sdram in self refresh and powerdown modes. self refresh mode allows the sdram to be put into a low power state while still retaining memory contents; since the sdram will continue to refresh itself even without clocks from the device. powerdown mode achieves even lower power, except the device must periodically wake the sdram up and issue refreshes if data retention is required. finally, note that the emifa does not support mobile sdram devices. table 6-17 shows the supported sdram configurations for emifa. 76 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-17. emifa supported sdram configurations (1) sdram emifa data total total memory memory number of bus size rows columns banks memory memory density data bus memories (bits) (mbits) (mbytes) (mbits) width (bits) 1 16 16 8 1 256 32 256 1 16 16 8 2 512 64 512 1 16 16 8 4 1024 128 1024 1 16 16 9 1 512 64 512 1 16 16 9 2 1024 128 1024 16 1 16 16 9 4 2048 256 2048 1 16 16 10 1 1024 128 1024 1 16 16 10 2 2048 256 2048 1 16 16 10 4 4096 512 4096 1 16 16 11 1 2048 256 2048 1 16 16 11 2 4096 512 4096 1 16 15 11 4 4096 512 4096 2 16 16 8 1 256 32 128 2 16 16 8 2 512 64 256 2 16 16 8 4 1024 128 512 2 16 16 9 1 512 64 256 2 16 16 9 2 1024 128 512 8 2 16 16 9 4 2048 256 1024 2 16 16 10 1 1024 128 512 2 16 16 10 2 2048 256 1024 2 16 16 10 4 4096 512 2048 2 16 16 11 1 2048 256 1024 2 16 16 11 2 4096 512 2048 2 16 15 11 4 4096 512 2048 (1) the shaded cells indicate configurations that are possible on the emifa interface but as of this writing sdram memories capable of supporting these densities are not available in the market. 6.10.3 emifa sdram loading limitations emifa supports sdram up to 100 mhz with up to two sdram or asynchronous memory loads. additional loads will limit the sdram operation to lower speeds and the maximum speed should be confirmed by board simulation using ibis models. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 77 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.10.4 external memory interface register descriptions table 6-18. external memory interface (emifa) registers byte address acronym register description 0x6800 0000 midr module id register 0x6800 0004 awcc asynchronous wait cycle configuration register 0x6800 0008 sdcr sdram configuration register 0x6800 000c sdrcr sdram refresh control register 0x6800 0010 ce2cfg asynchronous 1 configuration register 0x6800 0014 ce3cfg asynchronous 2 configuration register 0x6800 0018 ce4cfg asynchronous 3 configuration register 0x6800 001c ce5cfg asynchronous 4 configuration register 0x6800 0020 sdtimr sdram timing register 0x6800 003c sdsretr sdram self refresh exit timing register 0x6800 0040 intraw emifa interrupt raw register 0x6800 0044 intmsk emifa interrupt mask register 0x6800 0048 intmskset emifa interrupt mask set register 0x6800 004c intmskclr emifa interrupt mask clear register 0x6800 0060 nandfcr nand flash control register 0x6800 0064 nandfsr nand flash status register 0x6800 0070 nandf1ecc nand flash 1 ecc register (cs2 space) 0x6800 0074 nandf2ecc nand flash 2 ecc register (cs3 space) 0x6800 0078 nandf3ecc nand flash 3 ecc register (cs4 space) 0x6800 007c nandf4ecc nand flash 4 ecc register (cs5 space) 0x6800 00bc nand4biteccload nand flash 4-bit ecc load register 0x6800 00c0 nand4bitecc1 nand flash 4-bit ecc register 1 0x6800 00c4 nand4bitecc2 nand flash 4-bit ecc register 2 0x6800 00c8 nand4bitecc3 nand flash 4-bit ecc register 3 0x6800 00cc nand4bitecc4 nand flash 4-bit ecc register 4 0x6800 00d0 nanderradd1 nand flash 4-bit ecc error address register 1 0x6800 00d4 nanderradd2 nand flash 4-bit ecc error address register 2 0x6800 00d8 nanderrval1 nand flash 4-bit ecc error value register 1 0x6800 00dc nanderrval2 nand flash 4-bit ecc error value register 2 78 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.10.5 emifa electrical data/timing table 6-19 through table 6-22 assume testing over recommended operating conditions. table 6-19. timing requirements for emifa sdram interface 1.2v 1.1v 1.0v no. unit min max min max min max input setup time, read data valid on ema_d[15:0] before 19 t su(ema_dv-em_clkh) 2 3 3 ns ema_clk rising input hold time, read data valid on ema_d[15:0] after 20 t h(clkh-div) 1.6 1.6 1.6 ns ema_clk rising table 6-20. switching characteristics for emifa sdram interface 1.2v 1.1v 1.0v no. parameter unit min max min max min max 1 t c(clk) cycle time, emif clock ema_clk 10 15 20 ns 2 t w(clk) pulse width, emif clock ema_clk high or low 3 5 8 ns 3 t d(clkh-csv) delay time, ema_clk rising to ema_cs[0] valid 7 9.5 13 ns 4 t oh(clkh-csiv) output hold time, ema_clk rising to ema_cs[0] invalid 1 1 1 ns 5 t d(clkh-dqmv) delay time, ema_clk rising to ema_ we_dqm[1:0] valid 7 9.5 13 ns output hold time, ema_clk rising to ema_ we_dqm[1:0] 6 t oh(clkh-dqmiv) 1 1 1 ns invalid delay time, ema_clk rising to ema_a[12:0] and 7 t d(clkh-av) 7 9.5 13 ns ema_ba[1:0] valid output hold time, ema_clk rising to ema_a[12:0] and 8 t oh(clkh-aiv) 1 1 1 ns ema_ba[1:0] invalid 9 t d(clkh-dv) delay time, ema_clk rising to ema_d[15:0] valid 7 9.5 13 ns 10 t oh(clkh-div) output hold time, ema_clk rising to ema_d[15:0] invalid 1 1 1 ns 11 t d(clkh-rasv) delay time, ema_clk rising to ema_ras valid 7 9.5 13 ns 12 t oh(clkh-rasiv) output hold time, ema_clk rising to ema_ras invalid 1 1 1 ns 13 t d(clkh-casv) delay time, ema_clk rising to ema_cas valid 7 9.5 13 ns 14 t oh(clkh-casiv) output hold time, ema_clk rising to ema_cas invalid 1 1 1 ns 15 t d(clkh-wev) delay time, ema_clk rising to ema_we valid 7 9.5 13 ns 16 t oh(clkh-weiv) output hold time, ema_clk rising to ema_we invalid 1 1 1 ns 17 t dis(clkh-dhz) delay time, ema_clk rising to ema_d[15:0] tri-stated 7 9.5 13 ns 18 t ena(clkh-dlz) output hold time, ema_clk rising to ema_d[15:0] driving 1 1 1 ns copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 79 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 6-10. emifa basic sdram write operation figure 6-11. emifa basic sdram read operation 80 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 ema_clk ema_ba[1:0] ema_a[12:0]ema_d[15:0] 1 2 2 4 6 8 8 12 14 19 20 3 5 7 7 11 13 17 18 2 em_clk delay basic sdramread opera tion ema_cs[0] ema_we _dqm[1:0] ema_ras ema_cas ema_we ema_clk ema_ba[1:0] ema_a[12:0]ema_d[15:0] 1 2 2 4 6 8 8 12 10 16 3 5 7 7 11 13 15 9 basic sdramwrite opera tion ema_cs[0] ema_we _dqm[1:0] ema_ras ema_cas ema_we
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-21. timing requirements for emifa asynchronous memory interface (1) 1.2v 1.1v 1.0v no. unit min max min max min max reads and writes 13.3 e t c(clk) cycle time, emifa module clock 6.75 20 ns 3 2 t w(em_wait) pulse duration, em_wait assertion and deassertion 2e 2e 2e ns reads 12 t su(emdv-emoeh) setup time, em_d[15:0] valid before em_oe high 3 5 7 ns 13 t h(emoeh-emdiv) hold time, em_d[15:0] valid after em_oe high 0 0 0 ns setup time, em_wait asserted before end of strobe 14 t su (emoel-emwait) 4e+3 4e+3 4e+3 ns phase (2) writes setup time, em_wait asserted before end of strobe 28 t su (emwel-emwait) 4e+3 4e+3 4e+3 ns phase (2) (1) e = ema_clk period or in ns. ema_clk is selected either as sysclk3 or the pll0 output clock divided by 4.5. as an example, when sysclk3 is selected and set to 100mhz, e=10ns (2) setup before end of strobe phase (if no extended wait states are inserted) by which em_wait must be asserted to add extended wait states. figure 6-14 and figure 6-15 describe emif transactions that include extended wait states inserted during the strobe phase. however, cycles inserted as part of this extended wait period should not be counted; the 4e requirement is to the start of where the hold phase would begin if there were no extended wait cycles. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 81 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-22. switching characteristics for emifa asynchronous memory interface (1) (2) (3) 1.2v, 1.1v, 1.0v no. parameter unit min nom max reads and writes 1 t d(turnaround) turn around time (ta)*e - 3 (ta)*e (ta)*e + 3 ns reads emif read cycle time (ew = 0) (rs+rst+rh)*e - 3 (rs+rst+rh)*e (rs+rst+rh)*e + 3 ns 3 t c(emrcycle) emif read cycle time (ew = 1) (rs+rst+rh+ewc)*e - 3 (rs+rst+rh+ewc)*e (rs+rst+rh+ewc)*e + 3 ns output setup time, ema_ce[5:2] low to ema_oe low (ss = 0) (rs)*e-3 (rs)*e (rs)*e+3 ns 4 t su(emcel-emoel) output setup time, ema_ce[5:2] low to ema_oe low (ss = 1) -3 0 +3 ns output hold time, ema_oe high to ema_ce[5:2] high (ss = 0) (rh)*e - 3 (rh)*e (rh)*e + 3 ns 5 t h(emoeh-emceh) output hold time, ema_oe high to ema_ce[5:2] high (ss = 1) -3 0 +3 ns 6 t su(embav-emoel) output setup time, ema_ba[1:0] valid to ema_oe low (rs)*e-3 (rs)*e (rs)*e+3 ns 7 t h(emoeh-embaiv) output hold time, ema_oe high to ema_ba[1:0] invalid (rh)*e-3 (rh)*e (rh)*e+3 ns 8 t su(embav-emoel) output setup time, ema_a[13:0] valid to ema_oe low (rs)*e-3 (rs)*e (rs)*e+3 ns 9 t h(emoeh-emaiv) output hold time, ema_oe high to ema_a[13:0] invalid (rh)*e-3 (rh)*e (rh)*e+3 ns ema_oe active low width (ew = 0) (rst)*e-3 (rst)*e (rst)*e+3 ns 10 t w(emoel) ema_oe active low width (ew = 1) (rst+ewc)*e-3 (rst+ewc)*e (rst+ewc)*e+3 ns 11 t d(emwaith-emoeh) delay time from ema_wait deasserted to ema_oe high 3e-3 4e 4e+3 ns 28 t su(emarw-emoel) output setup time, ema_a_r w valid to ema_oe low (rs)*e-3 (rs)*e (rs)*e+3 ns 29 t h(emoeh-emarw) output hold time, ema_oe high to ema_a_r w invalid (rh)*e-3 (rh)*e (rh)*e+3 ns writes emif write cycle time (ew = 0) (ws+wst+wh)*e-3 (ws+wst+wh)*e (ws+wst+wh)*e+3 ns 15 t c(emwcycle) emif write cycle time (ew = 1) (ws+wst+wh+ewc)*e - 3 (ws+wst+wh+ewc)*e (ws+wst+wh+ewc)*e + 3 ns output setup time, ema_ce[5:2] low to ema_we low (ss = 0) (ws)*e - 3 (ws)*e (ws)*e + 3 ns 16 t su(emcel-emwel) output setup time, ema_ce[5:2] low to ema_we low (ss = 1) -3 0 +3 ns output hold time, ema_we high to ema_ce[5:2] high (ss = 0) (wh)*e-3 (wh)*e (wh)*e+3 ns 17 t h(emweh-emceh) output hold time, ema_we high to ema_ce[5:2] high (ss = 1) -3 0 +3 ns 18 t su(emdqmv-emwel) output setup time, ema_ba[1:0] valid to ema_we low (ws)*e-3 (ws)*e (ws)*e+3 ns 19 t h(emweh-emdqmiv) output hold time, ema_we high to ema_ba[1:0] invalid (wh)*e-3 (wh)*e (wh)*e+3 ns 20 t su(embav-emwel) output setup time, ema_ba[1:0] valid to ema_we low (ws)*e-3 (ws)*e (ws)*e+3 ns 21 t h(emweh-embaiv) output hold time, ema_we high to ema_ba[1:0] invalid (wh)*e-3 (wh)*e (wh)*e+3 ns 22 t su(emav-emwel) output setup time, ema_a[13:0] valid to ema_we low (ws)*e-3 (ws)*e (ws)*e+3 ns (1) ta = turn around, rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold, mewc = maximum external wait cycles. these parameters are programmed via the asynchronous bank and asynchronous wait cycle configuration registers. these support the following range of values: ta[4-1], rs[16-1], rst[64- 1], rh[8-1], ws[16-1], wst[64-1], wh[8-1], and mew[1-256]. (2) e = ema_clk period or in ns. ema_clk is selected either as sysclk3 or the pll0 output clock divided by 4.5. as an example, when sysclk3 is selected and set to 100mhz, e=10ns. (3) ewc = external wait cycles determined by ema_wait input signal. ewc supports the following range of values ewc[256-1]. note that the maximum wait time before timeout is specified by bit field mewc in the asynchronous wait cycle configuration register. 82 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-22. switching characteristics for emifa asynchronous memory interface (1) (2) (3) (continued) 1.2v, 1.1v, 1.0v no. parameter unit min nom max 23 t h(emweh-emaiv) output hold time, ema_we high to ema_a[13:0] invalid (wh)*e-3 (wh)*e (wh)*e+3 ns ema_we active low width (ew = 0) (wst)*e-3 (wst)*e (wst)*e+3 ns 24 t w(emwel) ema_we active low width (ew = 1) (wst+ewc)*e-3 (wst+ewc)*e (wst+ewc)*e+3 ns 25 t d(emwaith-emweh) delay time from ema_wait deasserted to ema_we high 3e-3 4e 4e+3 ns 26 t su(emdv-emwel) output setup time, ema_d[15:0] valid to ema_we low (ws)*e-3 (ws)*e (ws)*e+3 ns 27 t h(emweh-emdiv) output hold time, ema_we high to ema_d[15:0] invalid (wh)*e-3 (wh)*e (wh)*e+3 ns 30 t su(emarw-emwel) output setup time, ema_a_r w valid to ema_we low (ws)*e-3 (ws)*e (ws)*e+3 ns 31 t h(emweh-emarw) output hold time, ema_we high to ema_a_r w invalid (wh)*e-3 (wh)*e (wh)*e+3 ns copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 83 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 6-12. asynchronous memory read timing for emifa figure 6-13. asynchronous memory write timing for emifa 84 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 ema_cs[5:2] ema_ba[1:0] ema_a[22:0] ema_we ema_d[15:0] ema_oe 15 1 16 18 20 22 24 17 19 21 23 26 27 ema_ _dqm[1:0] we ema_a_rw 1 30 31 setup strobe hold ema_cs[5:2] ema_ba[1:0] 13 12 ema_a[22:0] ema_oe ema_d[15:0] ema_we 10 5 9 7 4 8 3 1 ema_ _dqm[1:0] we ema_a_rw 1 6 28 29 setup strobe hold
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-14. ema_wait read timing requirements figure 6-15. ema_wait write timing requirements copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 85 submit documentation feedback product folder links: am1802 ema_a[22:0] ema_cs[5:2] ema_ba[1:0] ema_d[15:0] ema_a_rw ema_we ema_wait ema_cs[5:2] 1 1 asserted deasserted 2 2 ema_ba[1:0] ema_a[22:0]ema_d[15:0] ema_oe ema_wait setup strobe extended due to ema_wait strobe hold 1 4 ema_a_rw
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.11 ddr2/mddr controller the ddr2/mddr memory controller is a dedicated interface to ddr2/mddr sdram. it supports jesd79-2a standard compliant ddr2 sdram devices and compliant mobile ddr sdram devices. the ddr2/mddr memory controller support the following features: ? jesd79-2a standard compliant ddr2 sdram ? mobile ddr sdram ? 256-mb memory space for ddr2 ? 256-mb memory space for mddr ? cas latencies: ? ddr2: 2, 3, 4 and 5 ? mddr: 2 and 3 ? internal banks: ? ddr2: 1, 2, 4 and 8 ? mddr:1, 2 and 4 ? burst length: 8 ? burst type: sequential ? 1 chip select (cs) signal ? page sizes: 256, 512, 1024 and 2048 ? sdram autoinitialization ? self-refresh mode ? partial array self-refresh (for mddr) ? power down mode ? prioritized refresh ? programmable refresh rate and backlog counter ? programmable timing parameters ? little endian 6.11.1 ddr2/mddr memory controller electrical data/timing table 6-23. switching characteristics over recommended operating conditions for ddr2/mddr memory controller no. parameter 1.2v 1.1v 1.0v unit min max min max min max ddr2 125 156 125 150 ? (1) ? (1) cycle time, 1 t c(ddr_clk) mhz ddr_clkp / ddr_clkn mddr 105 150 100 133 95 133 (1) ddr2 is not supported at this voltage operating point. 86 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.11.2 ddr2/mddr controller register description(s) table 6-24. ddr2/mddr controller registers byte address acronym register description 0xb000 0000 revid revision id register 0xb000 0004 sdrstat sdram status register 0xb000 0008 sdcr sdram configuration register 0xb000 000c sdrcr sdram refresh control register 0xb000 0010 sdtimr1 sdram timing register 1 0xb000 0014 sdtimr2 sdram timing register 2 0xb000 001c sdcr2 sdram configuration register 2 0xb000 0020 pbbpr peripheral bus burst priority register 0xb000 0040 pc1 performance counter 1 registers 0xb000 0044 pc2 performance counter 2 register 0xb000 0048 pcc performance counter configuration register 0xb000 004c pcmrs performance counter master region select register 0xb000 0050 pct performance counter time register 0xb000 00c0 irr interrupt raw register 0xb000 00c4 imr interrupt mask register 0xb000 00c8 imsr interrupt mask set register 0xb000 00cc imcr interrupt mask clear register 0xb000 00e4 drpyc1r ddr phy control register 1 0x01e2 c000 vtpio_ctl vtp io control register 6.11.3 ddr2/mddr interface this section provides the timing specification for the ddr2/mddr interface as a pcb design and manufacturing specification. the design rules constrain pcb trace length, pcb trace skew, signal integrity, cross-talk, and signal timing. these rules, when followed, result in a reliable ddr2/mddr memory system without the need for a complex timing closure process. for more information regarding guidelines for using this ddr2/mddr specification, understanding ti's pcb routing rule-based ddr2 timing specification ( spraav0 ). 6.11.3.1 ddr2/mddr interface schematic figure 6-16 shows the ddr2/mddr interface schematic for a single-memory ddr2/mddr system. the dual-memory system shown in figure 6-17 . pin numbers for the device can be obtained from the pin description section. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 87 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com (1) see figure 6-23 for dqgate routing specifications. (2) for ddr2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device vref pin. for mddr, these capacitors can be eliminated completely. (3) vref applies in the case of ddr2 memories. for mddr, the ddr_vref pin still needs to be connected to the divider circuit. figure 6-16. ddr2/mddr single-memory high level schematic 88 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 ddr2/mddr memory controller ddr_d[7] ddr2/mddr ddr_dqm[0] odt dq0dq7 ddr_d[8] ddr_d[15] dq8dq15 ldmldqs ldqs ddr_dqm[1] ddr_dqs[1] udmudqs udqs ddr_ba[0] ddr_ba[2] ba0ba2 ddr_a[0] ddr_a[13] a0 ddr_cs ddr_cas cs cas ddr_ras ddr_we ras we ddr_cke cke ddr_clkp ddr_clkn ckck ddr_dqgate0 ddr_dqgate1 ddr_zp ddr_vref 1 k 1% ddr_dvdd18 vref 1 k 1% 0.1 f 0.1 f 0.1 f (2) 0.1 f (2) 50 5 % t terminator, if desired. see terminator comments. dq7 a13 0.1 f 0.1 f t terminator, if desired. see terminator comments. ddr_d[0] nc t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t vref (3) t terminator, if desired. see terminator comments. 0.1 f (2) ddr_dqs[0] nc (1)
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 (1) see figure 6-23 for dqgate routing specifications. (2) for ddr2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device vref pin. for mddr, these capacitors can be eliminated completely. (3) vref applies in the case of ddr2 memories. for mddr, the ddr_vref pin still needs to be connected to the divider circuit. figure 6-17. ddr2/mddr dual-memory high level schematic copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 89 submit documentation feedback product folder links: am1802 ddr2/mddr memory controller ddr_d[0:7] lower byte ddr2/mddr ddr_dqm[0] ddr_dqs[0] odt dq0 dq7ba0ba2 ck ck dmdqs dqs cs cas ras ddr_ba[0:2] cke ba0ba2 ddr_a[0:13] ddr_clkp a0a13 ddr_clkn ddr_cs ck cs ddr_cas ddr_ras cas ras ddr_we we ddr_d[8:15] dqs dq0 dq7 ddr_dqgate0 ddr_dqgate1 t t t t t t t t t t t t t t ddr_zp vref (3) ddr_vref 1 k 1% ddr_dvdd18 vref 1 k 1% 0.1 f 0.1 f 0.1 f (2) 0.1 f (2) 0.1 f (2) 50 5 % t terminator, if desired. see terminator comments. odt a0a13 we vref upper byte ddr2/mddr ck ddr_cke cke t ddr_dqm1 dm t ddr_dqs1 dqs t nc nc (1)
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.11.3.2 compatible jedec ddr2/mddr devices table 6-25 shows the parameters of the jedec ddr2/mddr devices that are compatible with this interface. generally, the ddr2/mddr interface is compatible with x16 ddr2-400/mddr-200 speed grade ddr2/mddr devices. the device also supports jedec ddr2/mddr x8 devices in the dual chip configuration. in this case, one chip supplies the upper byte and the second chip supplies the lower byte. addresses and most control signals are shared just like regular dual chip memory configurations. table 6-25. compatible jedec ddr2/mddr devices no. parameter min max unit 1 jedec ddr2/mddr device speed grade (1) ddr2-400/mddr- 200 2 jedec ddr2/mddr device bit width x8 x16 bits 3 jedec ddr2/mddr device count (2) 1 2 devices (1) higher ddr2/mddr speed grades are supported due to inherent jedec ddr2/mddr backwards compatibility. (2) supported configurations are one 16-bit ddr2/mddr memory or two 8-bit ddr2/mddr memories 6.11.3.3 pcb stackup the minimum stackup required for routing the device is a six layer stack as shown in table 6-26 . additional layers may be added to the pcb stack up to accommodate other circuitry or to reduce the size of the pcb footprint.complete stack up specifications are provided in table 6-27 . table 6-26. device minimum pcb stack up layer type description 1 signal top routing mostly horizontal 2 plane ground 3 plane power 4 signal internal routing 5 plane ground 6 signal bottom routing mostly vertical table 6-27. pcb stack up specifications no. parameter min typ max unit 1 pcb routing/plane layers 6 2 signal routing layers 3 3 full ground layers under ddr2/mddr routing region 2 4 number of ground plane cuts allowed within ddr routing region 0 5 number of ground reference planes required for each ddr2/mddr routing layer 1 6 number of layers between ddr2/mddr routing layer and reference ground plane 0 7 pcb routing feature size 4 mils 8 pcb trace width w 4 mils 8 pcb bga escape via pad size 18 mils 9 pcb bga escape via hole size 8 mils 10 device bga pad size (1) 11 ddr2/mddr device bga pad size (2) 12 single ended impedance, zo 50 75 ? 13 impedance control (3) z-5 z z+5 ? (1) please refer to the flip chip ball grid array package reference guide ( spru811 ) for device bga pad size. (2) please refer to the ddr2/mddr device manufacturer documentation for the ddr2/mddr device bga pad size. (3) z is the nominal singled ended impedance selected for the pcb specified by item 12. 90 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.11.3.4 placement figure 6-17 shows the required placement for the device as well as the ddr2/mddr devices. the dimensions for figure 6-18 are defined in table 6-28 . the placement does not restrict the side of the pcb that the devices are mounted on. the ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. for single-memory ddr2/mddr systems, the second ddr2/mddr device is omitted from the placement. figure 6-18. device and ddr2/mddr device placement table 6-28. placement specifications (1) (2) no. parameter min max unit 1 x 1750 mils 2 y 1280 mils 3 y offset (3) 650 mils 4 clearance from non-ddr2/mddr signal to ddr2/mddr keepout region (4) 4 w (5) (1) see figure 6-18 for dimension definitions. (2) measurements from center of device to center of ddr2/mddr device. (3) for single memory systems it is recommended that y offset be as small as possible. (4) non-ddr2/mddr signals allowed within ddr2/mddr keepout region provided they are separated from ddr2/mddr routing layers by a ground plane. (5) w = pcb trace width as defined in table 6-27 . copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 91 submit documentation feedback product folder links: am1802 a1a1 x y offset recommended ddr2/mddr device orientation y y offset ddr2/mddr device ddr2/mddr controller
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.11.3.5 ddr2/mddr keep out region the region of the pcb used for the ddr2/mddr circuitry must be isolated from other signals. the ddr2/mddr keep out region is defined for this purpose and is shown in figure 6-19 . the size of this region varies with the placement and ddr routing. additional clearances required for the keep out region are shown in table 6-28 . figure 6-19. ddr2/mddr keepout region 92 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 a1a1 ddr2/mddr controller ddr2/mddr device region should encompass all ddr2/mddr circuitry and variesdepending on placement. non-ddr2/mddr signals should not be routed on the ddr signal layers within the ddr2/mddr keep out region. non-ddr2/mddr signals may be routed in the region provided they are routed on layers separated from ddr2/mddr signal layers by a ground layer. no breaks should be allowed in the reference ground layers in this region. in addition, the 1.8 v power plane should cover the entire keep out region.
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.11.3.6 bulk bypass capacitors bulk bypass capacitors are required for moderate speed bypassing of the ddr2/mddr and other circuitry. table 6-29 contains the minimum numbers and capacitance required for the bulk bypass capacitors. note that this table only covers the bypass needs of the device and ddr2/mddr interfaces. additional bulk bypass capacitance may be needed for other circuitry. table 6-29. bulk bypass capacitors no. parameter min max unit 1 ddr_dvdd18 supply bulk bypass capacitor count (1) 3 devices 2 ddr_dvdd18 supply bulk bypass total capacitance 30 f 3 ddr#1 bulk bypass capacitor count (1) 1 devices 4 ddr#1 bulk bypass total capacitance 22 f 5 ddr#2 bulk bypass capacitor count (1) (2) 1 devices 6 ddr#2 bulk bypass total capacitance (2) 22 f (1) these devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (hs) bypass caps. (2) only used on dual-memory systems. 6.11.3.7 high-speed bypass capacitors high-speed (hs) bypass capacitors are critical for proper ddr2/mddr interface operation. it is particularly important to minimize the parasitic series inductance of the hs bypass cap, device/ddr2/mddr power, and device/ddr2/mddr ground connections. table 6-30 contains the specification for the hs bypass capacitors as well as for the power connections on the pcb. table 6-30. high-speed bypass capacitors no. parameter min max unit 1 hs bypass capacitor package size (1) 0402 10 mils 2 distance from hs bypass capacitor to device being bypassed 250 mils 3 number of connection vias for each hs bypass capacitor 2 (2) vias 4 trace length from bypass capacitor contact to connection via 1 30 mils 5 number of connection vias for each ddr2/mddr device power or ground balls 1 vias 6 trace length from ddr2/mddr device power ball to connection via 35 mils 7 ddr_dvdd18 supply hs bypass capacitor count (3) 10 devices 8 ddr_dvdd18 supply hs bypass capacitor total capacitance 0.6 f 9 ddr#1 hs bypass capacitor count (3) 8 devices 10 ddr#1 hs bypass capacitor total capacitance 0.4 f 11 ddr#2 hs bypass capacitor count (3) (4) 8 devices 12 ddr#2 hs bypass capacitor total capacitance (4) 0.4 f (1) lxw, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor (2) an additional hs bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. (3) these devices should be placed as close as possible to the device being bypassed. (4) only used on dual-memory systems. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 93 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.11.3.8 net classes table 6-31 lists the clock net classes for the ddr2/mddr interface. table 6-32 lists the signal net classes, and associated clock net classes, for the signals in the ddr2/mddr interface. these net classes are used for the termination and routing rules that follow. table 6-31. clock net class definitions clock net class pin names ck ddr_clkp / ddr_clkn dqs0 ddr_dqs[0] dqs1 ddr_dqs[1] table 6-32. signal net class definitions associated clock signal net class net class pin names addr_ctrl ck ddr_ba[2:0], ddr_a[13:0], ddr_cs, ddr_cas, ddr_ras, ddr_we, ddr_cke d0 dqs0 ddr_d[7:0], ddr_dqm0 d1 dqs1 ddr_d[15:8], ddr_dqm1 dqgate ck, dqs0, dqs1 ddr_dqgate0, ddr_dqgate1 6.11.3.9 ddr2/mddr signal termination no terminations of any kind are required in order to meet signal integrity and overshoot requirements. serial terminators are permitted, if desired, to reduce emi risk; however, serial terminations are the only type permitted. table 6-33 shows the specifications for the series terminators. table 6-33. ddr2/mddr signal terminations (1) (2) (3) no. parameter min typ max unit 1 ck net class 0 10 ? 2 addr_ctrl net class 0 22 zo ? 3 data byte net classes (dqs[0], dqs[1], d0, d1) (4) 0 22 zo ? 4 dqgate net class (dqgate) 0 10 zo ? (1) only series termination is permitted, parallel or sst specifically disallowed. (2) terminator values larger than typical only recommended to address emi issues. (3) termination value should be uniform across net class. (4) when no termination is used on data lines (0 ? ), the ddr2/mddr devices must be programmed to operate in 60% strength mode. 94 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.11.3.10 vref routing vref is used as a reference by the input buffers of the ddr2/mddr memories as well as the device. vref is intended to be half the ddr2/mddr power supply voltage and should be created using a resistive divider as shown in figure 6-16 . other methods of creating vref are not recommended. figure 6-20 shows the layout guidelines for vref. figure 6-20. vref routing and topology copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 95 submit documentation feedback product folder links: am1802 a1 a1 ddr2/mddr device vref nominal minimum trace width is 20 mils vref bypass capacitor neck down to minimum in bga escape regions is acceptable. narrowing to accomodate via congestion for short distances is also acceptable. best performance is obtained if the width of vref is maximized. ddr2/mddr
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.11.3.11 ddr2/mddr ck and addr_ctrl routing figure 6-21 shows the topology of the routing for the ck and addr_ctrl net classes. the route is a balanced t as it is intended that the length of segments b and c be equal. in addition, the length of a should be maximized. figure 6-21. ck and addr_ctrl routing and topology table 6-34. ck and addr_ctrl routing specification no. parameter min typ max unit 1 center to center ck-ckn spacing (1) 2w (2) 2 ck a to b/a to c skew length mismatch (3) 25 mils 3 ck b to c skew length mismatch 25 mils 4 center to center ck to other ddr2/mddr trace spacing (1) 4w (2) 5 ck/addr_ctrl nominal trace length (4) caclm-50 caclm caclm+50 mils 6 addr_ctrl to ck skew length mismatch 100 mils 7 addr_ctrl to addr_ctrl skew length mismatch 100 mils 8 center to center addr_ctrl to other ddr2/mddr trace spacing (1) 4w (2) 9 center to center addr_ctrl to other addr_ctrl trace spacing (1) 3w (2) 10 addr_ctrl a to b/a to c skew length mismatch (3) 100 mils 11 addr_ctrl b to c skew length mismatch 100 mils (1) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (2) w = pcb trace width as defined in table 6-27 . (3) series terminator, if used, should be located closest to device. (4) caclm is the longest manhattan distance of the ck and addr_ctrl net classes. 96 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 a1 a1 c b a t ddr2/mddr controller
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-22 shows the topology and routing for the dqs and d net class; the routes are point to point. skew matching across bytes is not needed nor recommended. figure 6-22. dqs and d routing and topology table 6-35. dqs and d routing specification no. parameter min typ max unit 1 center to center dqs to other ddr2/mddr trace spacing (1) 4w (2) 2 dqs/d nominal trace length (3) (4) dqlm-50 dqlm dqlm+50 mils 3 d to dqs skew length mismatch (4) 100 mils 4 d to d skew length mismatch (4) 100 mils 5 center to center d to other ddr2/mddr trace spacing (1) (5) 4w (2) 6 center to center d to other d trace spacing (1) (6) 3w (2) (1) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (2) w = pcb trace width as defined in table 6-27 . (3) series terminator, if used, should be located closest to ddr. (4) there is no need and it is not recommended to skew match across data bytes, i.e., from dqs0 and data byte 0 to dqs1 and data byte 1. (5) d ' s from other dqs domains are considered other ddr2/mddr trace . (6) dqlm is the longest manhattan distance of each of the dqs and d net class. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 97 submit documentation feedback product folder links: am1802 a1 a1 e0 t e1 ddr2/mddr controller t
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 6-23 shows the routing for the dqgate net class. table 6-36 contains the routing specification. figure 6-23. dqgate routing table 6-36. dqgate routing specification no. parameter min typ max unit 1 dqgate length f ckb0b (1) 2 center to center dqgate to any other trace spacing 4w (2) 3 dqs/d nominal trace length dqlm-50 dqlm dqlm+50 mils 4 dqgate skew (3) 100 mils (1) ckb0b1 is the sum of the length of the ck net plus the average length of the dqs0 and dqs1 nets. (2) w = pcb trace width as defined in table 6-27 . (3) skew from ckb0b1 6.11.3.12 mddr/ddr2 boundary scan limitations due to ddr implementation and timing restrictions, it was not possible to place boundary scan cells between core logic and the io like boundary scan cells for other io. instead, the boundary scan cells are tapped-off to the ddr phy and there is the equivalent of a multiplexer inside the ddr phy which selects between functional and boundary scan paths. the implication for boundary scan is that the ddr pins will not support the sample function of the output enable cells on the ddr pins and this is a violation of ieee 1149.1. full extest and preload capability is still available. 98 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 a1a1 tt ddr2/mddr controller f
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.12 memory protection units the mpu performs memory protection checking. it receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. if allowed, the transfer is passed unmodified to its output bus (to the targeted address). if the transfer is illegal (fails the protection check) then the mpu does not pass the transfer to the output bus but rather services the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as well as generating an interrupt about the fault. the following features are supported by the mpu: ? provides memory protection for fixed and programmable address ranges. ? supports multiple programmable address region. ? supports secure and debug access privileges. ? supports read, write, and execute access privileges. ? supports privid(8) associations with ranges. ? generates an interrupt when there is a protection violation, and saves violating transfer parameters. ? mmr access is also protected. table 6-37. mpu1 configuration registers mpu1 acronym register description byte address 0x01e1 4000 revid revision id 0x01e1 4004 config configuration 0x01e1 4010 irawstat interrupt raw status/set 0x01e1 4014 ienstat interrupt enable status/clear 0x01e1 4018 ienset interrupt enable 0x01e1 401c ienclr interrupt enable clear 0x01e1 4020 - 0x01e1 41ff - reserved 0x01e1 4200 prog1_mpsar programmable range 1, start address 0x01e1 4204 prog1_mpear programmable range 1, end address 0x01e1 4208 prog1_mppa programmable range 1, memory page protection attributes 0x01e1 420c - 0x01e1 420f - reserved 0x01e1 4210 prog2_mpsar programmable range 2, start address 0x01e1 4214 prog2_mpear programmable range 2, end address 0x01e1 4218 prog2_mppa programmable range 2, memory page protection attributes 0x01e1 421c - 0x01e1 421f - reserved 0x01e1 4220 prog3_mpsar programmable range 3, start address 0x01e1 4224 prog3_mpear programmable range 3, end address 0x01e1 4228 prog3_mppa programmable range 3, memory page protection attributes 0x01e1 422c - 0x01e1 422f - reserved 0x01e1 4230 prog4_mpsar programmable range 4, start address 0x01e1 4234 prog4_mpear programmable range 4, end address 0x01e1 4238 prog4_mppa programmable range 4, memory page protection attributes 0x01e1 423c - 0x01e1 423f - reserved 0x01e1 4240 prog5_mpsar programmable range 5, start address 0x01e1 4244 prog5_mpear programmable range 5, end address 0x01e1 4248 prog5_mppa programmable range 5, memory page protection attributes 0x01e1 424c - 0x01e1 424f - reserved 0x01e1 4250 prog6_mpsar programmable range 6, start address 0x01e1 4254 prog6_mpear programmable range 6, end address 0x01e1 4258 prog6_mppa programmable range 6, memory page protection attributes 0x01e1 425c - 0x01e1 42ff - reserved copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 99 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-37. mpu1 configuration registers (continued) mpu1 acronym register description byte address 0x01e1 4300 fltaddrr fault address 0x01e1 4304 fltstat fault status 0x01e1 4308 fltclr fault clear 0x01e1 430c - 0x01e1 4fff - reserved table 6-38. mpu2 configuration registers mpu2 acronym register description byte address 0x01e1 5000 revid revision id 0x01e1 5004 config configuration 0x01e1 5010 irawstat interrupt raw status/set 0x01e1 5014 ienstat interrupt enable status/clear 0x01e1 5018 ienset interrupt enable 0x01e1 501c ienclr interrupt enable clear 0x01e1 5020 - 0x01e1 51ff - reserved 0x01e1 5200 prog1_mpsar programmable range 1, start address 0x01e1 5204 prog1_mpear programmable range 1, end address 0x01e1 5208 prog1_mppa programmable range 1, memory page protection attributes 0x01e1 520c - 0x01e1 520f - reserved 0x01e1 5210 prog2_mpsar programmable range 2, start address 0x01e1 5214 prog2_mpear programmable range 2, end address 0x01e1 5218 prog2_mppa programmable range 2, memory page protection attributes 0x01e1 521c - 0x01e1 521f - reserved 0x01e1 5220 prog3_mpsar programmable range 3, start address 0x01e1 5224 prog3_mpear programmable range 3, end address 0x01e1 5228 prog3_mppa programmable range 3, memory page protection attributes 0x01e1 522c - 0x01e1 522f - reserved 0x01e1 5230 prog4_mpsar programmable range 4, start address 0x01e1 5234 prog4_mpear programmable range 4, end address 0x01e1 5238 prog4_mppa programmable range 4, memory page protection attributes 0x01e1 523c - 0x01e1 523f - reserved 0x01e1 5240 prog5_mpsar programmable range 5, start address 0x01e1 5244 prog5_mpear programmable range 5, end address 0x01e1 5248 prog5_mppa programmable range 5, memory page protection attributes 0x01e1 524c - 0x01e1 524f - reserved 0x01e1 5250 prog6_mpsar programmable range 6, start address 0x01e1 5254 prog6_mpear programmable range 6, end address 0x01e1 5258 prog6_mppa programmable range 6, memory page protection attributes 0x01e1 525c - 0x01e1 525f - reserved 0x01e1 5260 prog7_mpsar programmable range 7, start address 0x01e1 5264 prog7_mpear programmable range 7, end address 0x01e1 5268 prog7_mppa programmable range 7, memory page protection attributes 0x01e1 526c - 0x01e1 526f - reserved 0x01e1 5270 prog8_mpsar programmable range 8, start address 0x01e1 5274 prog8_mpear programmable range 8, end address 0x01e1 5278 prog8_mppa programmable range 8, memory page protection attributes 0x01e1 527c - 0x01e1 527f - reserved 100 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-38. mpu2 configuration registers (continued) mpu2 acronym register description byte address 0x01e1 5280 prog9_mpsar programmable range 9, start address 0x01e1 5284 prog9_mpear programmable range 9, end address 0x01e1 5288 prog9_mppa programmable range 9, memory page protection attributes 0x01e1 528c - 0x01e1 528f - reserved 0x01e1 5290 prog10_mpsar programmable range 10, start address 0x01e1 5294 prog10_mpear programmable range 10, end address 0x01e1 5298 prog10_mppa programmable range 10, memory page protection attributes 0x01e1 529c - 0x01e1 529f - reserved 0x01e1 52a0 prog11_mpsar programmable range 11, start address 0x01e1 52a4 prog11_mpear programmable range 11, end address 0x01e1 52a8 prog11_mppa programmable range 11, memory page protection attributes 0x01e1 52ac - 0x01e1 52af - reserved 0x01e1 52b0 prog12_mpsar programmable range 12, start address 0x01e1 52b4 prog12_mpear programmable range 12, end address 0x01e1 52b8 prog12_mppa programmable range 12, memory page protection attributes 0x01e1 52bc - 0x01e1 52ff - reserved 0x01e1 5300 fltaddrr fault address 0x01e1 5304 fltstat fault status 0x01e1 5308 fltclr fault clear 0x01e1 530c - 0x01e1 5fff - reserved copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 101 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.13 mmc / sd / sdio (mmcsd0) 6.13.1 mmcsd peripheral description the device includes one mmcsd controller which is compliant with mmc v4.0, secure digital part 1 physical layer specification v1.1 and secure digital input output (sdio) v2.0 specifications. the mmc/sd controller has following features: ? multimediacard (mmc) ? secure digital (sd) memory card ? mmc/sd protocol support ? sd high capacity support ? sdio protocol support ? programmable clock frequency ? 512 bit read/write fifo to lower system overhead ? slave edma transfer capability the device mmc/sd controller does not support spi mode. 6.13.2 mmcsd peripheral register description(s) table 6-39. multimedia card/secure digital (mmc/sd) card controller registers mmcsd0 acronym register descsription byte address 0x01c4 0000 mmcctl mmc control register 0x01c4 0004 mmcclk mmc memory clock control register 0x01c4 0008 mmcst0 mmc status register 0 0x01c4 000c mmcst1 mmc status register 1 0x01c4 0010 mmcim mmc interrupt mask register 0x01c4 0014 mmctor mmc response time-out register 0x01c4 0018 mmctod mmc data read time-out register 0x01c4 001c mmcblen mmc block length register 0x01c4 0020 mmcnblk mmc number of blocks register 0x01c4 0024 mmcnblc mmc number of blocks counter register 0x01c4 0028 mmcdrr mmc data receive register 0x01c4 002c mmcdxr mmc data transmit register 0x01c4 0030 mmccmd mmc command register 0x01c4 0034 mmcarghl mmc argument register 0x01c4 0038 mmcrsp01 mmc response register 0 and 1 0x01c4 003c mmcrsp23 mmc response register 2 and 3 0x01c4 0040 mmcrsp45 mmc response register 4 and 5 0x01c4 0044 mmcrsp67 mmc response register 6 and 7 0x01c4 0048 mmcdrsp mmc data response register 0x01c4 0050 mmccidx mmc command index register 0x01c4 0064 sdioctl sdio control register 0x01c4 0068 sdiost0 sdio status register 0 0x01c4 006c sdioien sdio interrupt enable register 0x01c4 0070 sdioist sdio interrupt status register 0x01c4 0074 mmcfifoctl mmc fifo control register 102 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.13.3 mmc/sd electrical data/timing table 6-40 through table 6-41 assume testing over recommended operating conditions. table 6-40. timing requirements for mmc/sd (see figure 6-25 and figure 6-27 ) 1.2v 1.1v 1.0v no. unit min max min max min max t su(cmdv- 1 setup time, mmcsd_cmd valid before mmcsd_clk high 4 4 6 ns clkh) 2 t h(clkh-cmdv) hold time, mmcsd_cmd valid after mmcsd_clk high 2.5 2.5 2.5 ns 3 t su(datv-clkh) setup time, mmcsd_datx valid before mmcsd_clk high 4.5 5 6 ns 4 t h(clkh-datv) hold time, mmcsd_datx valid after mmcsd_clk high 2.5 2.5 2.5 ns table 6-41. switching characteristics for mmc/sd (see figure 6-24 through figure 6-27 ) 1.2v 1.1v 1.0v no. parameter unit min max min max min max 7 f (clk) operating frequency, mmcsd_clk 0 52 0 50 0 25 mhz 8 f (clk_id) identification mode frequency, mmcsd_clk 0 400 0 400 0 400 khz 9 t w(clkl) pulse width, mmcsd_clk low 6.5 6.5 10 ns 10 t w(clkh) pulse width, mmcsd_clk high 6.5 6.5 10 ns 11 t r(clk) rise time, mmcsd_clk 3 3 10 ns 12 t f(clk) fall time, mmcsd_clk 3 3 10 ns 13 t d(clkl-cmd) delay time, mmcsd_clk low to mmcsd_cmd transition -4 2.5 -4 3 -4 4 ns 14 t d(clkl-dat) delay time, mmcsd_clk low to mmcsd_datx transition -4 3.3 -4 3.5 -4 4 ns copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 103 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 6-24. mmc/sd host command timing figure 6-25. mmc/sd card response timing figure 6-26. mmc/sd host write timing figure 6-27. mmc/sd host read and card crc status timing 104 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 start d0 d1 dx end 7 mmcsd_clk mmcsd_datx 9 10 4 3 3 4 start d0 d1 dx end mmcsd_clk mmcsd_datx 7 14 14 10 9 14 14 start xmit valid valid valid end mmcsd_clk mmcsd_cmd 10 9 7 1 2 start xmit valid valid valid end mmcsd_clk mmcsd_cmd 13 7 10 9 13 13 13
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.14 multichannel audio serial port (mcasp) the mcasp serial port is specifically designed for multichannel audio applications. its key features are: ? flexible clock and frame sync generation logic and on-chip dividers ? up to sixteen transmit or receive data pins and serializers ? large number of serial data format options, including: ? tdm frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst) ? time slots of 8,12,16, 20, 24, 28, and 32 bits ? first bit delay 0, 1, or 2 clocks ? msb or lsb first bit order ? left- or right-aligned data words within time slots ? dit mode with 384-bit channel status and 384-bit user data registers ? extensive error checking and mute generation logic ? all unused pins gpio-capable ? transmit & receive fifo buffers allow the mcasp to operate at a higher sample rate by making it more tolerant to dma latency. ? dynamic adjustment of clock dividers ? clock divider value may be changed without resetting the mcasp figure 6-28. mcasp block diagram copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 105 submit documentation feedback product folder links: am1802 receive logic c lo ck /f ra m e g e n e ra to r state machine clock check and serializer 0serializer 1 serializer y gio control dit ram 384 c384 u optional tra n s m it f o rm a tte r receive f o rm a tte r tra n s m it l o g ic c lo ck /f ra m e g e n e ra to r state machine mcasp peripheral configuration bus mcasp dma bus (dedicated) ahclkrxaclkrx afsrx amuteinx amutex afsxx aclkxx ahclkxx axrx[0] axrx[1] axrx[y] pins function receive master clockreceive bit clock r e c e iv e l e ft/r ig h t c lo ck o r f ra m e s y n c tra n s m it m a s te r c lo ck tra n s m it b it c lo ck tra n s m it l e ft/r ig h t c lo ck o r f ra m e s y n c tra n s m it/r e c e iv e s e ria l d a ta p in tra n s m it/r e c e iv e s e ria l d a ta p in tra n s m it/r e c e iv e s e ria l d a ta p in error detection the mcasp does not have a dedicated amutein pin.
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.14.1 mcasp peripheral registers description(s) registers for the mcasp are summarized in table 6-42 . the registers are accessed through the peripheral configuration port. the receive buffer registers (rbuf) and transmit buffer registers (xbuf) can also be accessed through the dma port, as listed in table 6-43 registers for the mcasp audio fifo (afifo) are summarized in table 6-44 . note that the afifo write fifo (wfifo) and read fifo (rfifo) have independent control and status registers. the afifo control registers are accessed through the peripheral configuration port. table 6-42. mcasp registers accessed through peripheral configuration port byte address acronym register description 0x01d0 0000 rev revision identification register 0x01d0 0010 pfunc pin function register 0x01d0 0014 pdir pin direction register 0x01d0 0018 pdout pin data output register 0x01d0 001c pdin read returns: pin data input register 0x01d0 001c pdset writes affect: pin data set register (alternate write address: pdout) 0x01d0 0020 pdclr pin data clear register (alternate write address: pdout) 0x01d0 0044 gblctl global control register 0x01d0 0048 amute audio mute control register 0x01d0 004c dlbctl digital loopback control register 0x01d0 0050 ditctl dit mode control register 0x01d0 0060 receiver global control register: alias of gblctl, only receive bits are affected - allows receiver to rgblctl be reset independently from transmitter 0x01d0 0064 rmask receive format unit bit mask register 0x01d0 0068 rfmt receive bit stream format register 0x01d0 006c afsrctl receive frame sync control register 0x01d0 0070 aclkrctl receive clock control register 0x01d0 0074 ahclkrctl receive high-frequency clock control register 0x01d0 0078 rtdm receive tdm time slot 0-31 register 0x01d0 007c rintctl receiver interrupt control register 0x01d0 0080 rstat receiver status register 0x01d0 0084 rslot current receive tdm time slot register 0x01d0 0088 rclkchk receive clock check control register 0x01d0 008c revtctl receiver dma event control register 0x01d0 00a0 transmitter global control register. alias of gblctl, only transmit bits are affected - allows xgblctl transmitter to be reset independently from receiver 0x01d0 00a4 xmask transmit format unit bit mask register 0x01d0 00a8 xfmt transmit bit stream format register 0x01d0 00ac afsxctl transmit frame sync control register 0x01d0 00b0 aclkxctl transmit clock control register 0x01d0 00b4 ahclkxctl transmit high-frequency clock control register 0x01d0 00b8 xtdm transmit tdm time slot 0-31 register 0x01d0 00bc xintctl transmitter interrupt control register 0x01d0 00c0 xstat transmitter status register 0x01d0 00c4 xslot current transmit tdm time slot register 0x01d0 00c8 xclkchk transmit clock check control register 0x01d0 00cc xevtctl transmitter dma event control register 0x01d0 0100 ditcsra0 left (even tdm time slot) channel status register (dit mode) 0 0x01d0 0104 ditcsra1 left (even tdm time slot) channel status register (dit mode) 1 0x01d0 0108 ditcsra2 left (even tdm time slot) channel status register (dit mode) 2 106 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-42. mcasp registers accessed through peripheral configuration port (continued) byte address acronym register description 0x01d0 010c ditcsra3 left (even tdm time slot) channel status register (dit mode) 3 0x01d0 0110 ditcsra4 left (even tdm time slot) channel status register (dit mode) 4 0x01d0 0114 ditcsra5 left (even tdm time slot) channel status register (dit mode) 5 0x01d0 0118 ditcsrb0 right (odd tdm time slot) channel status register (dit mode) 0 0x01d0 011c ditcsrb1 right (odd tdm time slot) channel status register (dit mode) 1 0x01d0 0120 ditcsrb2 right (odd tdm time slot) channel status register (dit mode) 2 0x01d0 0124 ditcsrb3 right (odd tdm time slot) channel status register (dit mode) 3 0x01d0 0128 ditcsrb4 right (odd tdm time slot) channel status register (dit mode) 4 0x01d0 012c ditcsrb5 right (odd tdm time slot) channel status register (dit mode) 5 0x01d0 0130 ditudra0 left (even tdm time slot) channel user data register (dit mode) 0 0x01d0 0134 ditudra1 left (even tdm time slot) channel user data register (dit mode) 1 0x01d0 0138 ditudra2 left (even tdm time slot) channel user data register (dit mode) 2 0x01d0 013c ditudra3 left (even tdm time slot) channel user data register (dit mode) 3 0x01d0 0140 ditudra4 left (even tdm time slot) channel user data register (dit mode) 4 0x01d0 0144 ditudra5 left (even tdm time slot) channel user data register (dit mode) 5 0x01d0 0148 ditudrb0 right (odd tdm time slot) channel user data register (dit mode) 0 0x01d0 014c ditudrb1 right (odd tdm time slot) channel user data register (dit mode) 1 0x01d0 0150 ditudrb2 right (odd tdm time slot) channel user data register (dit mode) 2 0x01d0 0154 ditudrb3 right (odd tdm time slot) channel user data register (dit mode) 3 0x01d0 0158 ditudrb4 right (odd tdm time slot) channel user data register (dit mode) 4 0x01d0 015c ditudrb5 right (odd tdm time slot) channel user data register (dit mode) 5 0x01d0 0180 srctl0 serializer control register 0 0x01d0 0184 srctl1 serializer control register 1 0x01d0 0188 srctl2 serializer control register 2 0x01d0 018c srctl3 serializer control register 3 0x01d0 0190 srctl4 serializer control register 4 0x01d0 0194 srctl5 serializer control register 5 0x01d0 0198 srctl6 serializer control register 6 0x01d0 019c srctl7 serializer control register 7 0x01d0 01a0 srctl8 serializer control register 8 0x01d0 01a4 srctl9 serializer control register 9 0x01d0 01a8 srctl10 serializer control register 10 0x01d0 01ac srctl11 serializer control register 11 0x01d0 01b0 srctl12 serializer control register 12 0x01d0 01b4 srctl13 serializer control register 13 0x01d0 01b8 srctl14 serializer control register 14 0x01d0 01bc srctl15 serializer control register 15 copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 107 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-42. mcasp registers accessed through peripheral configuration port (continued) byte address acronym register description 0x01d0 0200 xbuf0 (1) transmit buffer register for serializer 0 0x01d0 0204 xbuf1 (1) transmit buffer register for serializer 1 0x01d0 0208 xbuf2 (1) transmit buffer register for serializer 2 0x01d0 020c xbuf3 (1) transmit buffer register for serializer 3 0x01d0 0210 xbuf4 (1) transmit buffer register for serializer 4 0x01d0 0214 xbuf5 (1) transmit buffer register for serializer 5 0x01d0 0218 xbuf6 (1) transmit buffer register for serializer 6 0x01d0 021c xbuf7 (1) transmit buffer register for serializer 7 0x01d0 0220 xbuf8 (1) transmit buffer register for serializer 8 0x01d0 0224 xbuf9 (1) transmit buffer register for serializer 9 0x01d0 0228 xbuf10 (1) transmit buffer register for serializer 10 0x01d0 022c xbuf11 (1) transmit buffer register for serializer 11 0x01d0 0230 xbuf12 (1) transmit buffer register for serializer 12 0x01d0 0234 xbuf13 (1) transmit buffer register for serializer 13 0x01d0 0238 xbuf14 (1) transmit buffer register for serializer 14 0x01d0 023c xbuf15 (1) transmit buffer register for serializer 15 0x01d0 0280 rbuf0 (2) receive buffer register for serializer 0 0x01d0 0284 rbuf1 (2) receive buffer register for serializer 1 0x01d0 0288 rbuf2 (2) receive buffer register for serializer 2 0x01d0 028c rbuf3 (2) receive buffer register for serializer 3 0x01d0 0290 rbuf4 (2) receive buffer register for serializer 4 0x01d0 0294 rbuf5 (2) receive buffer register for serializer 5 0x01d0 0298 rbuf6 (2) receive buffer register for serializer 6 0x01d0 029c rbuf7 (2) receive buffer register for serializer 7 0x01d0 02a0 rbuf8 (2) receive buffer register for serializer 8 0x01d0 02a4 rbuf9 (2) receive buffer register for serializer 9 0x01d0 02a8 rbuf10 (2) receive buffer register for serializer 10 0x01d0 02ac rbuf11 (2) receive buffer register for serializer 11 0x01d0 02b0 rbuf12 (2) receive buffer register for serializer 12 0x01d0 02b4 rbuf13 (2) receive buffer register for serializer 13 0x01d0 02b8 rbuf14 (2) receive buffer register for serializer 14 0x01d0 02bc rbuf15 (2) receive buffer register for serializer 15 (1) writes to xrbuf originate from peripheral configuration port only when xbusel = 1 in xfmt. (2) reads from xrbuf originate on peripheral configuration port only when rbusel = 1 in rfmt. table 6-43. mcasp registers accessed through dma port access byte acronym register description type address read 0x01d0 2000 rbuf receive buffer dma port address. cycles through receive serializers, skipping over transmit accesses serializers and inactive serializers. starts at the lowest serializer at the beginning of each time slot. reads from dma port only if xbusel = 0 in xfmt. write 0x01d0 2000 xbuf transmit buffer dma port address. cycles through transmit serializers, skipping over receive accesses and inactive serializers. starts at the lowest serializer at the beginning of each time slot. writes to dma port only if rbusel = 0 in rfmt. 108 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-44. mcasp afifo registers accessed through peripheral configuration port byte address acronym register description 0x01d0 1000 afiforev afifo revision identification register 0x01d0 1010 wfifoctl write fifo control register 0x01d0 1014 wfifosts write fifo status register 0x01d0 1018 rfifoctl read fifo control register 0x01d0 101c rfifosts read fifo status register 6.14.2 mcasp electrical data/timing 6.14.2.1 multichannel audio serial port 0 (mcasp0) timing table 6-45 and table 6-47 assume testing over recommended operating conditions (see figure 6-29 and figure 6-30 ). table 6-45. timing requirements for mcasp0 (1.2v, 1.1v) (1) (2) 1.2v 1.1v no. unit min max min max 1 t c(ahclkrx) cycle time, ahclkr/x 25 28 ns 2 t w(ahclkrx) pulse duration, ahclkr/x high or low 12.5 14 ns 3 t c(aclkrx) cycle time, aclkr/x ahclkr/x ext 25 (3) 28 (3) ns 4 t w(aclkrx) pulse duration, aclkr/w high or low ahclkr/x ext 12.5 14 ns ahclkr/x int 11.5 12 ns setup time, 5 t su(afsrx-aclkrx) ahclkr/x ext input 4 5 ns afsr/x input to aclkr/x (4) ahclkr/x ext output 4 5 ns ahclkr/x int -1 -2 ns hold time, 6 t h(aclkrx-afsrx) ahclkr/x ext input 1 1 ns afsr/x input after aclkr/x (4) ahclkr/x ext output 1 1 ns ahclkr/x int 11.5 12 ns setup time, 7 t su(axr-aclkrx) axr0[n] input to aclkr/x (4) (5) ahclkr/x ext 4 5 ns ahclkr/x int -1 -2 ns hold time, 8 t h(aclkrx-axr) ahclkr/x ext input 3 4 ns axr0[n] input after aclkr/x (4) (5) ahclkr/x ext output 3 4 ns (1) aclkx0 internal - mcasp0 aclkxctl.clkxm = 1, pdir.aclkx = 1 aclkx0 external input - mcasp0 aclkxctl.clkxm = 0, pdir.aclkx = 0 aclkx0 external output - mcasp0 aclkxctl.clkxm = 0, pdir.aclkx = 1 aclkr0 internal - mcasp0 aclkrctl.clkrm = 1, pdir.aclkr =1 aclkr0 external input - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 0 aclkr0 external output - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 1 (2) p = sysclk2 period (3) this timing is limited by the timing shown or 2p, whichever is greater. (4) mcasp0 aclkxctl.async=1: receiver is clocked by its own aclkr0 (5) mcasp0 aclkxctl.async=0: receiver is clocked by transmitter ' s aclkx0 copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 109 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-46. timing requirements for mcasp0 (1.0v) (1) (2) 1.0v no. unit min max 1 t c(ahclkrx) cycle time, ahclkr/x 35 ns 2 t w(ahclkrx) pulse duration, ahclkr/x high or low 17.5 ns 3 t c(aclkrx) cycle time, aclkr/x ahclkr/x ext 35 (3) ns 4 t w(aclkrx) pulse duration, aclkr/w high or low ahclkr/x ext 17.5 ns ahclkr/x int 16 ns setup time, 5 t su(afsrx-aclkrx) ahclkr/x ext input 5.5 ns afsr/x input to aclkr/x (4) ahclkr/x ext output 5.5 ns ahclkr/x int -2 ns hold time, 6 t h(aclkrx-afsrx) ahclkr/x ext input 1 ns afsr/x input after aclkr/x (4) ahclkr/x ext output 1 ns ahclkr/x int 16 ns setup time, 7 t su(axr-aclkrx) axr0[n] input to aclkr/x (4) (5) ahclkr/x ext 5.5 ns ahclkr/x int -2 ns hold time, 8 t h(aclkrx-axr) ahclkr/x ext input 5 ns axr0[n] input after aclkr/x (4) (5) ahclkr/x ext output 5 ns (1) aclkx0 internal - mcasp0 aclkxctl.clkxm = 1, pdir.aclkx = 1 aclkx0 external input - mcasp0 aclkxctl.clkxm = 0, pdir.aclkx = 0 aclkx0 external output - mcasp0 aclkxctl.clkxm = 0, pdir.aclkx = 1 aclkr0 internal - mcasp0 aclkrctl.clkrm = 1, pdir.aclkr =1 aclkr0 external input - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 0 aclkr0 external output - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 1 (2) p = sysclk2 period (3) this timing is limited by the timing shown or 2p, whichever is greater. (4) mcasp0 aclkxctl.async=1: receiver is clocked by its own aclkr0 (5) mcasp0 aclkxctl.async=0: receiver is clocked by transmitter ' s aclkx0 110 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-47. switching characteristics for mcasp0 (1.2v, 1.1v) (1) 1.2v 1.1v no. parameter unit min max min max 9 t c(ahclkrx) cycle time, ahclkr/x 25 28 ns 10 t w(ahclkrx) pulse duration, ahclkr/x high or low ah - 2.5 (2) ah - 2.5 (2) ns 11 t c(aclkrx) cycle time, aclkr/x aclkr/x int 25 (3) (4) 28 (3) (4) ns 12 t w(aclkrx) pulse duration, aclkr/x high or low aclkr/x int a - 2.5 (5) a - 2.5 (5) ns aclkr/x int -1 6 -1 8 ns delay time, aclkr/x transmit edge 13 t d(aclkrx-afsrx) aclkr/x ext input 2 13.5 2 14.5 ns to afsx/r output valid (6) aclkr/x ext output 2 13.5 2 14.5 ns aclkr/x int -1 6 -1 8 ns delay time, aclkx transmit edge to 14 t d(aclkx-axrv) aclkr/x ext input 2 13.5 2 15 ns axr output valid aclkr/x ext output 2 13.5 2 15 ns disable time, aclkr/x transmit aclkr/x int 0 6 0 8 ns 15 t dis(aclkx-axrhz) edge to axr high impedance aclkr/x ext 2 13.5 2 15 ns following last data bit (1) mcasp0 aclkx0 internal - aclkxctl.clkxm = 1, pdir.aclkx = 1 aclkx0 external input - mcasp0 aclkxctl.clkxm = 0, pdir.aclkx = 0 aclkx0 external output - mcasp0aclkxctl.clkxm = 0, pdir.aclkx = 1 aclkr0 internal - mcasp0 aclkr0ctl.clkrm = 1, pdir.aclkr =1 aclkr0 external input - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 0 aclkr0 external output - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 1 (2) ah = (ahclkr/x period)/2 in ns. for example, when ahclkr/x period is 25 ns, use ah = 12.5 ns. (3) p = sysclk2 period (4) this timing is limited by the timing shown or 2p, whichever is greater. (5) a = (aclkr/x period)/2 in ns. for example, when ahclkr/x period is 25 ns, use ah = 12.5 ns. (6) mcasp0 aclkxctl.async=1: receiver is clocked by its own aclkr0 table 6-48. switching characteristics for mcasp0 (1.0v) (1) 1.0v no. parameter unit min max 9 t c(ahclkrx) cycle time, ahclkr/x 35 ns 10 t w(ahclkrx) pulse duration, ahclkr/x high or low ah - 2.5 (2) ns 11 t c(aclkrx) cycle time, aclkr/x aclkr/x int 35 (3) (4) ns 12 t w(aclkrx) pulse duration, aclkr/x high or low aclkr/x int a - 2.5 (5) ns aclkr/x int -0.5 10 ns delay time, aclkr/x transmit edge to afsx/r output 13 t d(aclkrx-afsrx) aclkr/x ext input 2 19 ns valid (6) aclkr/x ext output 2 19 ns aclkr/x int -0.5 10 ns 14 t d(aclkx-axrv) delay time, aclkx transmit edge to axr output valid aclkr/x ext input 2 19 ns aclkr/x ext output 2 19 ns aclkr/x int 0 10 ns disable time, aclkr/x transmit edge to axr high 15 t dis(aclkx-axrhz) impedance following last data bit aclkr/x ext 2 19 ns (1) mcasp0 aclkx0 internal - aclkxctl.clkxm = 1, pdir.aclkx = 1 aclkx0 external input - mcasp0 aclkxctl.clkxm = 0, pdir.aclkx = 0 aclkx0 external output - mcasp0aclkxctl.clkxm = 0, pdir.aclkx = 1 aclkr0 internal - mcasp0 aclkr0ctl.clkrm = 1, pdir.aclkr =1 aclkr0 external input - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 0 aclkr0 external output - mcasp0 aclkrctl.clkrm = 0, pdir.aclkr = 1 (2) ah = (ahclkr/x period)/2 in ns. for example, when ahclkr/x period is 25 ns, use ah = 12.5 ns. (3) p = sysclk2 period (4) this timing is limited by the timing shown or 2p, whichever is greater. (5) a = (aclkr/x period)/2 in ns. for example, when ahclkr/x period is 25 ns, use ah = 12.5 ns. (6) mcasp0 aclkxctl.async=1: receiver is clocked by its own aclkr0 copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 111 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com a. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). b. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). figure 6-29. mcasp input timings 112 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 8 7 4 4 3 2 2 1 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay)afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay)afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data in/receive) 6 5 aclkr/x (clkrp = clkxp = 0) (a) aclkr/x (clkrp = clkxp = 1) (b)
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 a. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). b. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). figure 6-30. mcasp output timings copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 113 submit documentation feedback product folder links: am1802 15 14 13 13 13 13 13 13 13 12 12 11 10 10 9 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data out/t ransmit) aclkr/x (clkrp = clkxp = 0) (b) aclkr/x (clkrp = clkxp = 1) (a)
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.15 serial peripheral interface ports (spi0, spi1) figure 6-31 is a block diagram of the spi module, which is a simple shift register and buffer plus control logic. data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. the spi can operate either as a master, in which case, it initiates a transfer and drives the spix_clk pin, or as a slave. four clock phase and polarity options are supported as well as many data formatting options. figure 6-31. block diagram of spi module the spi supports 3-, 4-, and 5-pin operation with three basic pins (spix_clk, spix_simo, and spix_somi) and two optional pins ( spix_scs, spix_ena). the optional spix_scs (slave chip select) pin is most useful to enable in slave mode when there are other slave devices on the same spi port. the device will only shift data and drive the spix_somi pin when spix_scs is held low. in slave mode, spix_ena is an optional output. the spix_ena output provides the status of the internal transmit buffer (spidat0/1 registers). in four-pin mode with the enable option, spix_ena is asserted only when the transmit buffer is full, indicating that the slave is ready to begin another transfer. in five-pin mode, the spix_ena is additionally qualified by spix_scs being asserted. this allows a single handshake line to be shared by multiple slaves on the same spi bus. in master mode, the spix_ena pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts spix_ena. the addition of this handshake signal simplifies spi communications and, on average, increases spi bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. instead, each transfer can begin as soon as both the master and slave have actually serviced the previous spi transfer. 114 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 peripheral configuration bus interrupt and dma requests 16-bit shift register 16-bit buffer gpio control (all pins) state machine clock control spix_simospix_somi spix_ena spix_scs spix_clk
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-32. illustration of spi master-to-spi slave connection copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 115 submit documentation feedback product folder links: am1802 optional ? slave chip select optional enable (ready) sla ve spi master spi spix_simo spix_simo spix_somi spix_somi spix_clk spix_clk spix_ena spix_ena spix_scs spix_scs
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.15.1 spi peripheral registers description(s) table 6-49 is a list of the spi registers. table 6-49. spix configuration registers spi0 spi1 acronym description byte address byte address 0x01c4 1000 0x01f0 e000 spigcr0 global control register 0 0x01c4 1004 0x01f0 e004 spigcr1 global control register 1 0x01c4 1008 0x01f0 e008 spiint0 interrupt register 0x01c4 100c 0x01f0 e00c spilvl interrupt level register 0x01c4 1010 0x01f0 e010 spiflg flag register 0x01c4 1014 0x01f0 e014 spipc0 pin control register 0 (pin function) 0x01c4 1018 0x01f0 e018 spipc1 pin control register 1 (pin direction) 0x01c4 101c 0x01f0 e01c spipc2 pin control register 2 (pin data in) 0x01c4 1020 0x01f0 e020 spipc3 pin control register 3 (pin data out) 0x01c4 1024 0x01f0 e024 spipc4 pin control register 4 (pin data set) 0x01c4 1028 0x01f0 e028 spipc5 pin control register 5 (pin data clear) 0x01c4 102c 0x01f0 e02c reserved reserved - do not write to this register 0x01c4 1030 0x01f0 e030 reserved reserved - do not write to this register 0x01c4 1034 0x01f0 e034 reserved reserved - do not write to this register 0x01c4 1038 0x01f0 e038 spidat0 shift register 0 (without format select) 0x01c4 103c 0x01f0 e03c spidat1 shift register 1 (with format select) 0x01c4 1040 0x01f0 e040 spibuf buffer register 0x01c4 1044 0x01f0 e044 spiemu emulation register 0x01c4 1048 0x01f0 e048 spidelay delay register 0x01c4 104c 0x01f0 e04c spidef default chip select register 0x01c4 1050 0x01f0 e050 spifmt0 format register 0 0x01c4 1054 0x01f0 e054 spifmt1 format register 1 0x01c4 1058 0x01f0 e058 spifmt2 format register 2 0x01c4 105c 0x01f0 e05c spifmt3 format register 3 0x01c4 1060 0x01f0 e060 intvec0 interrupt vector for spi int0 0x01c4 1064 0x01f0 e064 intvec1 interrupt vector for spi int1 116 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.15.2 spi electrical data/timing 6.15.2.1 serial peripheral interface (spi) timing table 6-50 through table 6-65 assume testing over recommended operating conditions (see figure 6-33 through figure 6-36 ). table 6-50. general timing requirements for spi0 master modes (1) 1.2v 1.1v 1.0v no. unit min max min max min max 1 t c(spc)m cycle time, spi0_clk, all master modes 20 (2) 256p 30 (2) 256p 40 (2) 256p ns 2 t w(spch)m pulse width high, spi0_clk, all master modes 0.5m-1 0.5m-1 0.5m-1 ns 3 t w(spcl)m pulse width low, spi0_clk, all master modes 0.5m-1 0.5m-1 0.5m-1 ns polarity = 0, phase = 0, 5 5 6 to spi0_clk rising polarity = 0, phase = 1, -0.5m+5 -0.5m+5 -0.5m+6 delay, initial data bit valid on to spi0_clk rising 4 t d(simo_spc)m spi0_simo after initial edge ns polarity = 1, phase = 0, on spi0_clk (3) 5 5 6 to spi0_clk falling polarity = 1, phase = 1, -0.5m+5 -0.5m+5 -0.5m+6 to spi0_clk falling polarity = 0, phase = 0, 5 5 6 from spi0_clk rising polarity = 0, phase = 1, 5 5 6 delay, subsequent bits valid from spi0_clk falling 5 t d(spc_simo)m on spi0_simo after transmit ns polarity = 1, phase = 0, edge of spi0_clk 5 5 6 from spi0_clk falling polarity = 1, phase = 1, 5 5 6 from spi0_clk rising polarity = 0, phase = 0, 0.5m-3 0.5m-3 0.5m-3 from spi0_clk falling polarity = 0, phase = 1, 0.5m-3 0.5m-3 0.5m-3 output hold time, spi0_simo from spi0_clk rising 6 t oh(spc_simo)m valid after receive edge of ns polarity = 1, phase = 0, spi0_clk 0.5m-3 0.5m-3 0.5m-3 from spi0_clk rising polarity = 1, phase = 1, 0.5m-3 0.5m-3 0.5m-3 from spi0_clk falling polarity = 0, phase = 0, 1.5 1.5 1.5 to spi0_clk falling polarity = 0, phase = 1, 1.5 1.5 1.5 input setup time, spi0_somi to spi0_clk rising 7 t su(somi_spc)m valid before receive edge of ns polarity = 1, phase = 0, spi0_clk 1.5 1.5 1.5 to spi0_clk rising polarity = 1, phase = 1, 1.5 1.5 1.5 to spi0_clk falling polarity = 0, phase = 0, 4 4 5 from spi0_clk falling polarity = 0, phase = 1, 4 4 5 input hold time, spi0_somi from spi0_clk rising 8 t ih(spc_somi)m valid after receive edge of ns polarity = 1, phase = 0, spi0_clk 4 4 5 from spi0_clk rising polarity = 1, phase = 1, 4 4 5 from spi0_clk falling (1) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (2) this timing is limited by the timing shown or 3p, whichever is greater. (3) first bit may be msb or lsb depending upon spi configuration. mo(0) refers to first bit and mo(n) refers to last bit output on spi0_simo. mi(0) refers to the first bit input and mi(n) refers to the last bit input on spi0_somi. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 117 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-51. general timing requirements for spi0 slave modes (1) 1.2v 1.1v 1.0v no. unit min max min max min max 9 t c(spc)s cycle time, spi0_clk, all slave modes 40 (2) 50 (2) 60 (2) ns 10 t w(spch)s pulse width high, spi0_clk, all slave modes 18 22 27 ns 11 t w(spcl)s pulse width low, spi0_clk, all slave modes 18 22 27 ns polarity = 0, phase = 0, 2p 2p 2p to spi0_clk rising polarity = 0, phase = 1, setup time, transmit data 2p 2p 2p to spi0_clk rising written to spi before initial 12 t su(somi_spc)s ns clock edge from polarity = 1, phase = 0, 2p 2p 2p master. (3) (4) to spi0_clk falling polarity = 1, phase = 1, 2p 2p 2p to spi0_clk falling polarity = 0, phase = 0, 17 20 27 from spi0_clk rising polarity = 0, phase = 1, 17 20 27 delay, subsequent bits valid from spi0_clk falling 13 t d(spc_somi)s on spi0_somi after ns polarity = 1, phase = 0, transmit edge of spi0_clk 17 20 27 from spi0_clk falling polarity = 1, phase = 1, 17 20 27 from spi0_clk rising polarity = 0, phase = 0, 0.5s-6 0.5s-16 0.5s-20 from spi0_clk falling polarity = 0, phase = 1, 0.5s-6 0.5s-16 0.5s-20 output hold time, from spi0_clk rising 14 t oh(spc_somi)s spi0_somi valid after ns polarity = 1, phase = 0, receive edge of spi0_clk 0.5s-6 0.5s-16 0.5s-20 from spi0_clk rising polarity = 1, phase = 1, 0.5s-6 0.5s-16 0.5s-20 from spi0_clk falling polarity = 0, phase = 0, 1.5 1.5 1.5 to spi0_clk falling polarity = 0, phase = 1, 1.5 1.5 1.5 input setup time, to spi0_clk rising 15 t su(simo_spc)s spi0_simo valid before ns polarity = 1, phase = 0, receive edge of spi0_clk 1.5 1.5 1.5 to spi0_clk rising polarity = 1, phase = 1, 1.5 1.5 1.5 to spi0_clk falling polarity = 0, phase = 0, 4 4 5 from spi0_clk falling polarity = 0, phase = 1, 4 4 5 input hold time, from spi0_clk rising 16 t ih(spc_simo)s spi0_simo valid after ns polarity = 1, phase = 0, receive edge of spi0_clk 4 4 5 from spi0_clk rising polarity = 1, phase = 1, 4 4 5 from spi0_clk falling (1) p = sysclk2 period; s = t c(spc)s (spi slave bit clock period) (2) this timing is limited by the timing shown or 3p, whichever is greater. (3) first bit may be msb or lsb depending upon spi configuration. so(0) refers to first bit and so(n) refers to last bit output on spi0_somi. si(0) refers to the first bit input and si(n) refers to the last bit input on spi0_simo. (4) measured from the termination of the write of new data to the spi module, in analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the spi module by the cpu. 118 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-52. additional spi0 master timings, 4-pin enable option (1) (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 3p+5 3p+5 3p+6 to spi0_clk rising polarity = 0, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 to spi0_clk rising delay from slave assertion of spi0_ena 17 t d(ena_spc)m ns active to first spi0_clk from master. (4) polarity = 1, phase = 0, 3p+5 3p+5 3p+6 to spi0_clk falling polarity = 1, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 to spi0_clk falling polarity = 0, phase = 0, 0.5m+p+5 0.5m+p+5 0.5m+p+6 from spi0_clk falling polarity = 0, phase = 1, p+5 p+5 p+6 max delay for slave to deassert spi0_ena from spi0_clk falling 18 t d(spc_ena)m after final spi0_clk edge to ensure ns polarity = 1, phase = 0, master does not begin the next transfer. (5) 0.5m+p+5 0.5m+p+5 0.5m+p+6 from spi0_clk rising polarity = 1, phase = 1, p+5 p+5 p+6 from spi0_clk rising (1) these parameters are in addition to the general timings for spi master modes ( table 6-50 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four master clocking modes. (4) in the case where the master spi is ready with new data before spi0_ena assertion. (5) in the case where the master spi is ready with new data before spi0_en a deassertion. table 6-53. additional spi0 master timings, 4-pin chip select option (1) (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 2p-1 2p-2 2p-3 to spi0_clk rising polarity = 0, phase = 1, 0.5m+2p-1 0.5m+2p-2 0.5m+2p-3 to spi0_clk rising delay from spi0_scs active to first 19 t d(scs_spc)m ns spi0_clk (4) (5) polarity = 1, phase = 0, 2p-1 2p-2 2p-3 to spi0_clk falling polarity = 1, phase = 1, 0.5m+2p-1 0.5m+2p-2 0.5m+2p-3 to spi0_clk falling (1) these parameters are in addition to the general timings for spi master modes ( table 6-50 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four master clocking modes. (4) in the case where the master spi is ready with new data before spi0_scs assertion. (5) this delay can be increased under software control by the register bit field spidelay.c2tdelay[4:0]. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 119 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-53. additional spi0 master timings, 4-pin chip select option (1) (2) (3) (continued) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 0.5m+p-1 0.5m+p-2 0.5m+p-3 from spi0_clk falling polarity = 0, phase = 1, p-1 p-2 p-3 from spi0_clk falling delay from final spi0_clk edge to master 20 t d(spc_scs)m ns deasserting spi0_scs (6) (7) polarity = 1, phase = 0, 0.5m+p-1 0.5m+p-2 0.5m+p-3 from spi0_clk rising polarity = 1, phase = 1, p-1 p-2 p-3 from spi0_clk rising (6) except for modes when spidat1.cshold is enabled and there is additional data to transmit. in this case, spi0_scs will remain asserted. (7) this delay can be increased under software control by the register bit field spidelay.t2cdelay[4:0]. table 6-54. additional spi0 master timings, 5-pin option (1) (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 0.5m+p+5 0.5m+p+5 0.5m+p+6 from spi0_clk falling polarity = 0, phase = 1, max delay for slave to deassert p+5 p+5 p+6 from spi0_clk falling spi0_ena after final spi0_clk 18 t d(spc_ena)m ns edge to ensure master does not polarity = 1, phase = 0, 0.5m+p+5 0.5m+p+5 0.5m+p+6 begin the next transfer. (4) from spi0_clk rising polarity = 1, phase = 1, p+5 p+5 p+6 from spi0_clk rising polarity = 0, phase = 0, 0.5m+p-2 0.5m+p-2 0.5m+p-3 from spi0_clk falling polarity = 0, phase = 1, p-2 p-2 p-3 delay from final spi0_clk edge to from spi0_clk falling 20 t d(spc_scs)m master deasserting spi0_scs (5) ns polarity = 1, phase = 0, (6) 0.5m+p-2 0.5m+p-2 0.5m+p-3 from spi0_clk rising polarity = 1, phase = 1, p-2 p-2 p-3 from spi0_clk rising max delay for slave spi to drive spi0_ena valid after master 21 t d(scsl_enal)m asserts spi0_scs to delay the master from beginning the c2tdelay+p c2tdelay+p c2tdelay+p ns next transfer, (1) these parameters are in addition to the general timings for spi master modes ( table 6-51 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four master clocking modes. (4) in the case where the master spi is ready with new data before spi0_ena deassertion. (5) except for modes when spidat1.cshold is enabled and there is additional data to transmit. in this case, spi0_scs will remain asserted. (6) this delay can be increased under software control by the register bit field spidelay.t2cdelay[4:0]. 120 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-54. additional spi0 master timings, 5-pin option (1) (2) (3) (continued) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 2p-2 2p-2 2p-3 to spi0_clk rising polarity = 0, phase = 1, 0.5m+2p-2 0.5m+2p-2 0.5m+2p-3 to spi0_clk rising delay from spi0_scs active to 22 t d(scs_spc)m ns first spi0_clk (7) (8) (9) polarity = 1, phase = 0, 2p-2 2p-2 2p-3 to spi0_clk falling polarity = 1, phase = 1, 0.5m+2p-2 0.5m+2p-2 0.5m+2p-3 to spi0_clk falling polarity = 0, phase = 0, 3p+5 3p+5 3p+6 to spi0_clk rising polarity = 0, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 to spi0_clk rising delay from assertion of spi0_ena 23 t d(ena_spc)m ns low to first spi0_clk edge. (10) polarity = 1, phase = 0, 3p+5 3p+5 3p+6 to spi0_clk falling polarity = 1, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 to spi0_clk falling (7) if spi0_ena is asserted immediately such that the transmission is not delayed by spi0_ena. (8) in the case where the master spi is ready with new data before spi0_scs assertion. (9) this delay can be increased under software control by the register bit field spidelay.c2tdelay[4:0]. (10) if spi0_ena was initially deasserted high and spi0_clk is delayed. table 6-55. additional spi0 slave timings, 4-pin enable option (1) (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 1.5p-3 2.5p+17.5 1.5p-3 2.5p+20 1.5p-3 2.5p+27 from spi0_clk falling polarity = 0, phase = 1, - 0.5m+1.5p-3 - 0.5m+2.5p+17.5 - 0.5m+1.5p-3 - 0.5m+2.5p+20 - 0.5m+1.5p-3 - 0.5m+2.5p+27 from spi0_clk falling delay from final spi0_clk edge 24 t d(spc_enah)s ns to slave deasserting spi0_ena. polarity = 1, phase = 0, 1.5p-3 2.5p+17.5 1.5p-3 2.5p+20 1.5p-3 2.5p+27 from spi0_clk rising polarity = 1, phase = 1, - 0.5m+1.5p-3 - 0.5+2.5p+17.5 - 0.5m+1.5p-3 - 0.5+2.5p+20 - 0.5m+1.5p-3 - 0.5+2.5p+27 from spi0_clk rising (1) these parameters are in addition to the general timings for spi slave modes ( table 6-51 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four slave clocking modes. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 121 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-56. additional spi0 slave timings, 4-pin chip select option (1) (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max required delay from spi0_scs asserted at slave to first spi0_clk edge 25 t d(scsl_spc)s p + 1.5 p + 1.5 p + 1.5 ns at slave. polarity = 0, phase = 0, 0.5m+p+4 0.5m+p+4 0.5m+p+5 from spi0_clk falling polarity = 0, phase = 1, p+4 p+4 p+5 from spi0_clk falling required delay from final spi0_clk edge 26 t d(spc_scsh)s ns before spi0_scs is deasserted. polarity = 1, phase = 0, 0.5m+p+4 0.5m+p+4 0.5m+p+5 from spi0_clk rising polarity = 1, phase = 1, p+4 p+4 p+5 from spi0_clk rising 27 t ena(scsl_somi)s delay from master asserting spi0_scs to slave driving spi0_somi valid p+17.5 p+20 p+27 ns 28 t dis(scsh_somi)s delay from master deasserting spi0_scs to slave 3-stating spi0_somi p+17.5 p+20 p+27 ns (1) these parameters are in addition to the general timings for spi slave modes ( table 6-51 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four slave clocking modes. table 6-57. additional spi0 slave timings, 5-pin option (1) (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max required delay from spi0_scs asserted at slave to first 25 t d(scsl_spc)s p + 1.5 p + 1.5 p + 1.5 ns spi0_clk edge at slave. polarity = 0, phase = 0, 0.5m+p+4 0.5m+p+4 0.5m+p+5 from spi0_clk falling polarity = 0, phase = 1, p+4 p+4 p+5 required delay from final from spi0_clk falling 26 t d(spc_scsh)s spi0_clk edge before spi0_scs ns polarity = 1, phase = 0, is deasserted. 0.5m+p+4 0.5m+p+4 0.5m+p+5 from spi0_clk rising polarity = 1, phase = 1, p+4 p+4 p+5 from spi0_clk rising delay from master asserting spi0_scs to slave driving 27 t ena(scsl_somi)s p+17.5 p+20 p+27 ns spi0_somi valid delay from master deasserting spi0_scs to slave 3-stating 28 t dis(scsh_somi)s p+17.5 p+20 p+27 ns spi0_somi delay from master deasserting spi0_scs to slave driving 29 t ena(scsl_ena)s 17.5 20 27 ns spi0_ena valid (1) these parameters are in addition to the general timings for spi slave modes ( table 6-51 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four slave clocking modes. 122 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-57. additional spi0 slave timings, 5-pin option (1) (2) (3) (continued) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 2.5p+17.5 2.5p+20 2.5p+27 from spi0_clk falling polarity = 0, phase = 1, delay from final clock receive 2.5p+17.5 2.5p+20 2.5p+27 from spi0_clk rising edge on spi0_clk to slave 3- 30 t dis(spc_ena)s ns stating or driving high polarity = 1, phase = 0, 2.5p+17.5 2.5p+20 2.5p+27 spi0_ena. (4) from spi0_clk rising polarity = 1, phase = 1, 2.5p+17.5 2.5p+20 2.5p+27 from spi0_clk falling (4) spi0_ena is driven low after the transmission completes if the spiint0.enable_highz bit is programmed to 0. otherwise it is tri-stated. if tri-stated, an external pullup resistor should be used to provide a valid level to the master. this option is useful when tying several spi slave devices to a single master. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 123 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-58. general timing requirements for spi1 master modes (1) 1.2v 1.1v 1.0v no. unit min max min max min max 1 t c(spc)m cycle time, spi1_clk, all master modes 20 (2) 256p 30 (2) 256p 40 (2) 256p ns 2 t w(spch)m pulse width high, spi1_clk, all master modes 0.5m-1 0.5m-1 0.5m-1 ns 3 t w(spcl)m pulse width low, spi1_clk, all master modes 0.5m-1 0.5m-1 0.5m-1 ns polarity = 0, phase = 0, 5 5 6 to spi1_clk rising polarity = 0, phase = 1, -0.5m+5 -0.5m+5 -0.5m+6 delay, initial data bit valid on to spi1_clk rising 4 t d(simo_spc)m spi1_simo to initial edge on ns polarity = 1, phase = 0, spi1_clk (3) 5 5 6 to spi1_clk falling polarity = 1, phase = 1, -0.5m+5 -0.5m+5 -0.5m+6 to spi1_clk falling polarity = 0, phase = 0, 5 5 6 from spi1_clk rising polarity = 0, phase = 1, 5 5 6 delay, subsequent bits valid on from spi1_clk falling 5 t d(spc_simo)m spi1_simo after transmit edge ns polarity = 1, phase = 0, of spi1_clk 5 5 6 from spi1_clk falling polarity = 1, phase = 1, 5 5 6 from spi1_clk rising polarity = 0, phase = 0, 0.5m-3 0.5m-3 0.5m-3 from spi1_clk falling polarity = 0, phase = 1, 0.5m-3 0.5m-3 0.5m-3 output hold time, spi1_simo from spi1_clk rising 6 t oh(spc_simo)m valid after receive edge of ns polarity = 1, phase = 0, spi1_clk 0.5m-3 0.5m-3 0.5m-3 from spi1_clk rising polarity = 1, phase = 1, 0.5m-3 0.5m-3 0.5m-3 from spi1_clk falling polarity = 0, phase = 0, 1.5 1.5 1.5 to spi1_clk falling polarity = 0, phase = 1, 1.5 1.5 1.5 input setup time, spi1_somi to spi1_clk rising 7 t su(somi_spc)m valid before receive edge of ns polarity = 1, phase = 0, spi1_clk 1.5 1.5 1.5 to spi1_clk rising polarity = 1, phase = 1, 1.5 1.5 1.5 to spi1_clk falling polarity = 0, phase = 0, 4 5 6 from spi1_clk falling polarity = 0, phase = 1, 4 5 6 input hold time, spi1_somi from spi1_clk rising 8 t ih(spc_somi)m valid after receive edge of ns polarity = 1, phase = 0, spi1_clk 4 5 6 from spi1_clk rising polarity = 1, phase = 1, 4 5 6 from spi1_clk falling (1) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (2) this timing is limited by the timing shown or 3p, whichever is greater. (3) first bit may be msb or lsb depending upon spi configuration. mo(0) refers to first bit and mo(n) refers to last bit output on spi1_simo. mi(0) refers to the first bit input and mi(n) refers to the last bit input on spi1_somi. 124 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-59. general timing requirements for spi1 slave modes (1) 1.2v 1.1v 1.0v no. unit min max min max min max 9 t c(spc)s cycle time, spi1_clk, all slave modes 40 (2) 50 (2) 60 (2) ns 10 t w(spch)s pulse width high, spi1_clk, all slave modes 18 22 27 ns 11 t w(spcl)s pulse width low, spi1_clk, all slave modes 18 22 27 ns polarity = 0, phase = 0, 2p 2p 2p to spi1_clk rising polarity = 0, phase = 1, setup time, transmit data 2p 2p 2p to spi1_clk rising written to spi before initial 12 t su(somi_spc)s ns clock edge from polarity = 1, phase = 0, 2p 2p 2p master. (3) (4) to spi1_clk falling polarity = 1, phase = 1, 2p 2p 2p to spi1_clk falling polarity = 0, phase = 0, 15 17 19 from spi1_clk rising polarity = 0, phase = 1, 15 17 19 delay, subsequent bits valid from spi1_clk falling 13 t d(spc_somi)s on spi1_somi after transmit ns polarity = 1, phase = 0, edge of spi1_clk 15 17 19 from spi1_clk falling polarity = 1, phase = 1, 15 17 19 from spi1_clk rising polarity = 0, phase = 0, 0.5s-4 0.5s-10 0.5s-12 from spi1_clk falling polarity = 0, phase = 1, 0.5s-4 0.5s-10 0.5s-12 output hold time, spi1_somi from spi1_clk rising 14 t oh(spc_somi)s valid after receive edge of ns polarity = 1, phase = 0, spi1_clk 0.5s-4 0.5s-10 0.5s-12 from spi1_clk rising polarity = 1, phase = 1, 0.5s-4 0.5s-10 0.5s-12 from spi1_clk falling polarity = 0, phase = 0, 1.5 1.5 1.5 to spi1_clk falling polarity = 0, phase = 1, 1.5 1.5 1.5 input setup time, spi1_simo to spi1_clk rising 15 t su(simo_spc)s valid before receive edge of ns polarity = 1, phase = 0, spi1_clk 1.5 1.5 1.5 to spi1_clk rising polarity = 1, phase = 1, 1.5 1.5 1.5 to spi1_clk falling polarity = 0, phase = 0, 4 5 6 from spi1_clk falling polarity = 0, phase = 1, 4 5 6 input hold time, spi1_simo from spi1_clk rising 16 t ih(spc_simo)s valid after receive edge of ns polarity = 1, phase = 0, spi1_clk 4 5 6 from spi1_clk rising polarity = 1, phase = 1, 4 5 6 from spi1_clk falling (1) p = sysclk2 period; s = t c(spc)s (spi slave bit clock period) (2) this timing is limited by the timing shown or 3p, whichever is greater. (3) first bit may be msb or lsb depending upon spi configuration. so(0) refers to first bit and so(n) refers to last bit output on spi1_somi. si(0) refers to the first bit input and si(n) refers to the last bit input on spi1_simo. (4) measured from the termination of the write of new data to the spi module, in analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the spi module by the cpu. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 125 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-60. additional (1) spi1 master timings, 4-pin enable option (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 3p+5 3p+5 3p+6 to spi1_clk rising delay from slave polarity = 0, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 assertion of to spi1_clk rising 17 t d(en a_spc)m spi1_ena active to ns polarity = 1, phase = 0, first spi1_clk from 3p+5 3p+5 3p+6 to spi1_clk falling master. (4) polarity = 1, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 to spi1_clk falling polarity = 0, phase = 0, 0.5m+p+5 0.5m+p+5 0.5m+p+6 from spi1_clk falling max delay for slave to polarity = 0, phase = 1, deassert spi1_ena p+5 p+5 p+6 from spi1_clk falling after final spi1_clk 18 t d(spc_ena)m ns edge to ensure polarity = 1, phase = 0, 0.5m+p+5 0.5m+p+5 0.5m+p+6 master does not begin from spi1_clk rising the next transfer. (5) polarity = 1, phase = 1, p+5 p+5 p+6 from spi1_clk rising (1) these parameters are in addition to the general timings for spi master modes ( table 6-58 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four master clocking modes. (4) in the case where the master spi is ready with new data before spi1_ena assertion. (5) in the case where the master spi is ready with new data before spi1_ena deassertion. table 6-61. additional (1) spi1 master timings, 4-pin chip select option (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 2p-1 2p-5 2p-6 to spi1_clk rising polarity = 0, phase = 1, delay from 0.5m+2p-1 0.5m+2p-5 0.5m+2p-6 to spi1_clk rising spi1_scs active 19 t d(scs_spc)m ns to first polarity = 1, phase = 0, 2p-1 2p-5 2p-6 spi1_clk (4) (5) to spi1_clk falling polarity = 1, phase = 1, 0.5m+2p-1 0.5m+2p-5 0.5m+2p-6 to spi1_clk falling polarity = 0, phase = 0, 0.5m+p-1 0.5m+p-5 0.5m+p-6 from spi1_clk falling delay from final polarity = 0, phase = 1, p-1 p-5 p-6 spi1_clk edge to from spi1_clk falling 20 t d(spc_scs)m master ns polarity = 1, phase = 0, deasserting 0.5m+p-1 0.5m+p-5 0.5m+p-6 from spi1_clk rising spi1_scs (6) (7) polarity = 1, phase = 1, p-1 p-5 p-6 from spi1_clk rising (1) these parameters are in addition to the general timings for spi master modes ( table 6-58 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four master clocking modes. (4) in the case where the master spi is ready with new data before spi1_scs assertion. (5) this delay can be increased under software control by the register bit field spidelay.c2tdelay[4:0]. (6) except for modes when spidat1.cshold is enabled and there is additional data to transmit. in this case, spi1_scs will remain asserted. (7) this delay can be increased under software control by the register bit field spidelay.t2cdelay[4:0]. 126 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-62. additional (1) spi1 master timings, 5-pin option (2) (3) 1.3v, 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 0.5m+p+5 0.5m+p+5 0.5m+p+6 from spi1_clk falling polarity = 0, phase = 1, max delay for slave to deassert p+5 p+5 p+6 from spi1_clk falling spi1_ena after final spi1_clk 18 t d(spc_ena)m ns edge to ensure master does not polarity = 1, phase = 0, 0.5m+p+5 0.5m+p+5 0.5m+p+6 begin the next transfer. (4) from spi1_clk rising polarity = 1, phase = 1, p+5 p+5 p+6 from spi1_clk rising polarity = 0, phase = 0, 0.5m+p-1 0.5m+p-5 0.5m+p-6 from spi1_clk falling polarity = 0, phase = 1, p-1 p-5 p-6 from spi1_clk falling delay from final spi1_clk edge to 20 t d(spc_scs)m ns master deasserting spi1_scs (5) (6) polarity = 1, phase = 0, 0.5m+p-1 0.5m+p-5 0.5m+p-6 from spi1_clk rising polarity = 1, phase = 1, p-1 p-5 p-6 from spi1_clk rising max delay for slave spi to drive spi1_ena valid after master 21 t d(scsl_enal)m asserts spi1_scs to delay the c2tdelay+p c2tdelay+p c2tdelay+p ns master from beginning the next transfer, polarity = 0, phase = 0, 2p-1 2p-5 2p-6 to spi1_clk rising polarity = 0, phase = 1, 0.5m+2p-1 0.5m+2p-5 0.5m+2p-6 to spi1_clk rising delay from spi1_scs active to first 22 t d(scs_spc)m ns spi1_clk (7) (8) (9) polarity = 1, phase = 0, 2p-1 2p-5 2p-6 to spi1_clk falling polarity = 1, phase = 1, 0.5m+2p-1 0.5m+2p-5 0.5m+2p-6 to spi1_clk falling (1) these parameters are in addition to the general timings for spi master modes ( table 6-59 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four master clocking modes. (4) in the case where the master spi is ready with new data before spi1_ena deassertion. (5) except for modes when spidat1.cshold is enabled and there is additional data to transmit. in this case, spi1_scs will remain asserted. (6) this delay can be increased under software control by the register bit field spidelay.t2cdelay[4:0]. (7) if spi1_ena is asserted immediately such that the transmission is not delayed by spi1_ena. (8) in the case where the master spi is ready with new data before spi1_scs assertion. (9) this delay can be increased under software control by the register bit field spidelay.c2tdelay[4:0]. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 127 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-62. additional (1) spi1 master timings, 5-pin option (2) (3) (continued) 1.3v, 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 3p+5 3p+5 3p+6 to spi1_clk rising polarity = 0, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 to spi1_clk rising delay from assertion of spi1_ena 23 t d(ena_spc)m ns low to first spi1_clk edge. (10) polarity = 1, phase = 0, 3p+5 3p+5 3p+6 to spi1_clk falling polarity = 1, phase = 1, 0.5m+3p+5 0.5m+3p+5 0.5m+3p+6 to spi1_clk falling (10) if spi1_ena was initially deasserted high and spi1_clk is delayed. table 6-63. additional (1) spi1 slave timings, 4-pin enable option (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 1.5p-3 2.5p+15 1.5p-10 2.5p+17 1.5p-12 2.5p+19 from spi1_clk falling polarity = 0, phase = 1, -0.5m+1.5p-3 -0.5m+2.5p+15 -0.5m+1.5p-10 -0.5m+2.5p+17 -0.5m+1.5p-12 -0.5m+2.5p+19 from spi1_clk falling delay from final spi1_clk edge to 24 t d(spc_enah)s ns slave deasserting spi1_ena. polarity = 1, phase = 0, 1.5p-3 2.5p+15 1.5p-10 2.5p+17 1.5p-12 2.5p+19 from spi1_clk rising polarity = 1, phase = 1, -0.5m+1.5p-3 -0.5m+2.5p+15 -0.5m+1.5p-10 -0.5m+2.5p+17 -0.5m+1.5p-12 -0.5m+2.5p+19 from spi1_clk rising (1) these parameters are in addition to the general timings for spi slave modes ( table 6-59 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four slave clocking modes. table 6-64. additional (1) spi1 slave timings, 4-pin chip select option (2) (3) 1.3v, 1.2v 1.1v 1.0v no. parameter unit min max min max min max required delay from spi1_scs asserted at slave to first spi1_clk edge at 25 t d(scsl_spc)s p+1.5 p+1.5 p+1.5 ns slave. (1) these parameters are in addition to the general timings for spi slave modes ( table 6-59 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four slave clocking modes. 128 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-64. additional (1) spi1 slave timings, 4-pin chip select option (2) (3) (continued) 1.3v, 1.2v 1.1v 1.0v no. parameter unit min max min max min max polarity = 0, phase = 0, 0.5m+p+4 0.5m+p+5 0.5m+p+6 from spi1_clk falling polarity = 0, phase = 1, p+4 p+5 p+6 from spi1_clk falling required delay from final spi1_clk edge 26 t d(spc_scsh)s ns before spi1_scs is deasserted. polarity = 1, phase = 0, 0.5m+p+4 0.5m+p+5 0.5m+p+6 from spi1_clk rising polarity = 1, phase = 1, p+4 p+5 p+6 from spi1_clk rising 27 t ena(scsl_somi)s delay from master asserting spi1_scs to slave driving spi1_somi valid p+15 p+17 p+19 ns 28 t dis(scsh_somi)s delay from master deasserting spi1_scs to slave 3-stating spi1_somi p+15 p+17 p+19 ns copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 129 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-65. additional (1) spi1 slave timings, 5-pin option (2) (3) 1.2v 1.1v 1.0v no. parameter unit min max min max min max required delay from spi1_scs asserted at slave to 25 t d(scsl_spc)s p+1.5 p+1.5 p+1.5 ns first spi1_clk edge at slave. polarity = 0, phase = 0, 0.5m+p+4 0.5m+p+5 0.5m+p+6 from spi1_clk falling polarity = 0, phase = 1, p+4 p+5 p+6 required delay from final from spi1_clk falling 26 t d(spc_scsh)s spi1_clk edge before ns polarity = 1, phase = 0, spi1_scs is deasserted. 0.5m+p+4 0.5m+p+5 0.5m+p+6 from spi1_clk rising polarity = 1, phase = 1, p+4 p+5 p+6 from spi1_clk rising t ena(scsl_somi) delay from master asserting spi1_scs to slave 27 p+15 p+17 p+19 ns s driving spi1_somi valid delay from master deasserting spi1_scs to slave 3- 28 t dis(scsh_somi)s p+15 p+17 p+19 ns stating spi1_somi delay from master deasserting spi1_scs to slave 29 t ena(scsl_ena)s 15 17 19 ns driving spi1_ena valid polarity = 0, phase = 0, 2.5p+15 2.5p+17 2.5p+19 from spi1_clk falling polarity = 0, phase = 1, delay from final clock 2.5p+15 2.5p+17 2.5p+19 from spi1_clk rising receive edge on spi1_clk 30 t dis(spc_ena)s ns to slave 3-stating or driving polarity = 1, phase = 0, 2.5p+15 2.5p+17 2.5p+19 high spi1_ena. (4) from spi1_clk rising polarity = 1, phase = 1, 2.5p+15 2.5p+17 2.5p+19 from spi1_clk falling (1) these parameters are in addition to the general timings for spi slave modes ( table 6-59 ). (2) p = sysclk2 period; m = t c(spc)m (spi master bit clock period) (3) figure shows only polarity = 0, phase = 0 as an example. table gives parameters for all four slave clocking modes. (4) spi1_ena is driven low after the transmission completes if the spiint0.enable_highz bit is programmed to 0. otherwise it is tri- stated. if tri-stated, an external pullup resistor should be used to provide a valid level to the master. this option is useful when tying several spi slave devices to a single master. 130 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-33. spi timings ? master mode copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 131 submit documentation feedback product folder links: am1802 spix_clk spix_simospix_somi spix_clk spix_simospix_somi spix_clk spix_simospix_somi spix_clk spix_simospix_somi mo(0) mo(1) mo(n?1) mo(n) mi(0) mi(1) mi(n?1) mi(n) mo(0) mo(1) mo(n?1) mo(n) mi(0) mi(1) mi(n?1) mi(n) mo(0) mo(1) mo(n?1) mo(n) mi(0) mi(1) mi(n?1) mi(n) mo(0) mo(1) mo(n?1) mo(n) mi(0) mi(1) mi(n?1) mi(n) 6 6 7 7 7 7 8 8 8 8 3 2 6 1 4 4 4 4 5 5 5 6 master modepolarity = 0 phase = 0 master mode polarity = 0 phase = 1 master modepolarity = 1 phase = 0 master mode polarity = 1 phase = 1 5
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 6-34. spi timings ? slave mode 132 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 spix_clk spix_simo spix_somi spix_clk spix_simospix_somi spix_clk spix_simospix_somi spix_clk spix_simospix_somi si(0) si(1) si(n?1) si(n) so(0) so(1) so(n?1) so(n) si(0) si(1) si(n?1) si(n) so(0) so(1) so(n?1) so(n) si(0) si(1) si(n?1) si(n) so(0) so(1) so(n?1) so(n) si(0) si(1) si(n?1) si(n) so(0) so(1) so(n?1) so(n) 14 14 15 15 15 15 16 16 16 16 11 10 14 9 12 12 12 12 13 13 13 13 14 sla ve mode polarity = 0 phase = 0 sla ve mode polarity = 0 phase = 1sla ve mode polarity = 1 phase = 0 sla ve mode polarity = 1 phase = 1
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-35. spi timings ? master mode (4-pin and 5-pin) copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 133 submit documentation feedback product folder links: am1802 master mode 4 pin with chip select spix_clk spix_simospix_somi spix_ena spix_clk spix_simospix_somi spix_scs spix_clk spix_simospix_somi spix_ena spix_scs mo(0) mo(1) mo(n?1) mo(n) mi(0) mi(1) mi(n?1) mi(n) mo(0) mo(1) mo(n?1) mo(n) mi(0) mi(1) mi(n?1) mi(n) mo(0) mo(1) mo(n?1) mo(n) mi(0) mi(1) mi(n?1) mi(n) 17 19 21 22 23 20 18 20 18 master mode 4 pin with enable master mode 5 pin a. deselected is programmable either high or 3?st a te (requires external pullup) desel (a) desel (a)
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 6-36. spi timings ? slave mode (4-pin and 5-pin) 134 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 27 spix_clk spix_somispix_simo spix_ena spix_clk spix_somispix_simo spix_scs spix_clk spix_somispix_simo spix_ena spix_scs so(0) so(1) so(n?1) so(n) si(0) si(1) si(n?1) si(n) so(0) so(1) so(n?1) so(n) si(0) si(1) si(n?1) si(n) so(0) so(1) so(n?1) so(n) si(0) si(1) si(n?1) si(n) 24 26 28 26 30 28 25 25 27 29 sla ve mode 4 pin with enable sla ve mode 4 pin with chip select sla ve mode 5 pin desel (a) desel (a) a. deselected is programmable either high or 3?st a te (requires external pullup)
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.16 inter-integrated circuit serial ports (i2c) 6.16.1 i2c device-specific information i2c port supports: ? compatible with philips ? i2c specification revision 2.1 (january 2000) ? fast mode up to 400 kbps (no fail-safe i/o buffers) ? noise filter to remove noise 50 ns or less ? seven- and ten-bit device addressing modes ? master (transmit/receive) and slave (transmit/receive) functionality ? events: dma, interrupt, or polling ? general-purpose i/o capability if not used as i2c figure 6-37 is block diagram of the device i2c module. figure 6-37. i2c module block diagram copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 135 submit documentation feedback product folder links: am1802 peripheral configuration bus noise filter noise filter clock prescaler i2cpscx prescalerregister bit clock generator i2cclkhx clock dividehigh register i2cclklx clock dividelow register control i2ccoarx own addressregister i2csarx slave addressregister i2ccmdrx mode register i2cemdrx extended moderegister i2ccntx data countregister i2cpid1 peripheral idregister 1 i2cpid2 peripheral idregister 2 transmit i2cxsrx t ransmit shift register i2cdxrx t ransmit buffer receive i2cdrrx receive buffer i2crsrx receive shiftregister i2cx_scli2cx_sda control interrupt/dma i2cierx interrupt enableregister i2cstrx interrupt statusregister i2csrcx interrupt sourceregister control i2cpfunc pin functionregister i2cpdir pin directionregister i2cpdin pin data inregister i2cpdout pin data outregister i2cpdset pin data setregister i2cpdclr pin data clearregister interrupt dma requests
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.16.2 i2c peripheral registers description(s) table 6-66 is the list of the i2c registers. table 6-66. inter-integrated circuit (i2c) registers i2c0 acronym register description byte address 0x01c2 2000 icoar i2c own address register 0x01c2 2004 icimr i2c interrupt mask register 0x01c2 2008 icstr i2c interrupt status register 0x01c2 200c icclkl i2c clock low-time divider register 0x01c2 2010 icclkh i2c clock high-time divider register 0x01c2 2014 iccnt i2c data count register 0x01c2 2018 icdrr i2c data receive register 0x01c2 201c icsar i2c slave address register 0x01c2 2020 icdxr i2c data transmit register 0x01c2 2024 icmdr i2c mode register 0x01c2 2028 icivr i2c interrupt vector register 0x01c2 202c icemdr i2c extended mode register 0x01c2 2030 icpsc i2c prescaler register 0x01c2 2034 revid1 i2c revision identification register 1 0x01c2 2038 revid2 i2c revision identification register 2 0x01c2 2048 icpfunc i2c pin function register 0x01c2 204c icpdir i2c pin direction register 0x01c2 2050 icpdin i2c pin data in register 0x01c2 2054 icpdout i2c pin data out register 0x01c2 2058 icpdset i2c pin data set register 0x01c2 205c icpdclr i2c pin data clear register 136 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.16.3 i2c electrical data/timing 6.16.3.1 inter-integrated circuit (i2c) timing table 6-67 and table 6-68 assume testing over recommended operating conditions (see figure 6-38 and figure 6-39 ). table 6-67. timing requirements for i2c input 1.2v, 1.1v, 1.0v no. standard mode fast mode unit min max min max 1 t c(scl) cycle time, i2cx_scl 10 2.5 s 2 t su(sclh-sdal) setup time, i2cx_scl high before i2cx_sda low 4.7 0.6 s 3 t h(scll-sdal) hold time, i2cx_scl low after i2cx_sda low 4 0.6 s 4 t w(scll) pulse duration, i2cx_scl low 4.7 1.3 s 5 t w(sclh) pulse duration, i2cx_scl high 4 0.6 s 6 t su(sda-sclh) setup time, i2cx_sda before i2cx_scl high 250 100 ns 7 t h(sda-scll) hold time, i2cx_sda after i2cx_scl low 0 0 0.9 s 8 t w(sdah) pulse duration, i2cx_sda high 4.7 1.3 s 9 t r(sda) rise time, i2cx_sda 1000 20 + 0.1c b 300 ns 10 t r(scl) rise time, i2cx_scl 1000 20 + 0.1c b 300 ns 11 t f(sda) fall time, i2cx_sda 300 20 + 0.1c b 300 ns 12 t f(scl) fall time, i2cx_scl 300 20 + 0.1c b 300 ns 13 t su(sclh-sdah) setup time, i2cx_scl high before i2cx_sda high 4 0.6 s 14 t w(sp) pulse duration, spike (must be suppressed) n/a 0 50 ns 15 c b capacitive load for each bus line 400 400 pf table 6-68. switching characteristics for i2c (1) 1.2v, 1.1v, 1.0v no. parameter standard mode fast mode unit min max min max 16 t c(scl) cycle time, i2cx_scl 10 2.5 s 17 t su(sclh-sdal) setup time, i2cx_scl high before i2cx_sda low 4.7 0.6 s 18 t h(sdal-scll) hold time, i2cx_scl low after i2cx_sda low 4 0.6 s 19 t w(scll) pulse duration, i2cx_scl low 4.7 1.3 s 20 t w(sclh) pulse duration, i2cx_scl high 4 0.6 s 21 t su(sdav-sclh) setup time, i2cx_sda valid before i2cx_scl high 250 100 ns 22 t h(scll-sdav) hold time, i2cx_sda valid after i2cx_scl low 0 0 0.9 s 23 t w(sdah) pulse duration, i2cx_sda high 4.7 1.3 s 28 t su(sclh-sdah) setup time, i2cx_scl high before i2cx_sda high 4 0.6 s (1) i2c must be configured correctly to meet the timings in table 6-68 . copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 137 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com figure 6-38. i2c receive timings figure 6-39. i2c transmit timings 138 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop i2cx_sda i2cx_scl 16 26 24 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop i2cx_sda i2cx_scl 1 11 9
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.17 universal asynchronous receiver/transmitter (uart) each uart has the following features: ? 16-byte storage space for both the transmitter and receiver fifos ? 1, 4, 8, or 14 byte selectable receiver fifo trigger level for autoflow control and dma ? dma signaling capability for both received and transmitted data ? programmable auto-rts and auto-cts for autoflow control ? programmable baud rate up to 12 mbaud ? programmable oversampling options of x13 and x16 ? frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates ? prioritized interrupts ? programmable serial data formats ? 5, 6, 7, or 8-bit characters ? even, odd, or no parity bit generation and detection ? 1, 1.5, or 2 stop bit generation ? false start bit detection ? line break generation and detection ? internal diagnostic capabilities ? loopback controls for communications link fault isolation ? break, parity, overrun, and framing error simulation ? modem control functions (cts, rts) the uart registers are listed in section 6.17.1 6.17.1 uart peripheral registers description(s) table 6-69 is the list of uart registers. table 6-69. uart registers uart0 uart1 uart2 acronym register description byte address byte address byte address 0x01c4 2000 0x01d0 c000 0x01d0 d000 rbr receiver buffer register (read only) 0x01c4 2000 0x01d0 c000 0x01d0 d000 thr transmitter holding register (write only) 0x01c4 2004 0x01d0 c004 0x01d0 d004 ier interrupt enable register 0x01c4 2008 0x01d0 c008 0x01d0 d008 iir interrupt identification register (read only) 0x01c4 2008 0x01d0 c008 0x01d0 d008 fcr fifo control register (write only) 0x01c4 200c 0x01d0 c00c 0x01d0 d00c lcr line control register 0x01c4 2010 0x01d0 c010 0x01d0 d010 mcr modem control register 0x01c4 2014 0x01d0 c014 0x01d0 d014 lsr line status register 0x01c4 2018 0x01d0 c018 0x01d0 d018 msr modem status register 0x01c4 201c 0x01d0 c01c 0x01d0 d01c scr scratchpad register 0x01c4 2020 0x01d0 c020 0x01d0 d020 dll divisor lsb latch 0x01c4 2024 0x01d0 c024 0x01d0 d024 dlh divisor msb latch 0x01c4 2028 0x01d0 c028 0x01d0 d028 revid1 revision identification register 1 0x01c4 2030 0x01d0 c030 0x01d0 d030 pwremu_mgmt power and emulation management register 0x01c4 2034 0x01d0 c034 0x01d0 d034 mdr mode definition register copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 139 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.17.2 uart electrical data/timing table 6-70. timing requirements for uart receive (1) (see figure 6-40 ) 1.2v, 1.1v, 1.0v no. unit min max 4 t w(urxdb) pulse duration, receive data bit (rxdn) 0.96u 1.05u ns 5 t w(urxsb) pulse duration, receive start bit 0.96u 1.05u ns (1) u = uart baud time = 1/programmed baud rate. table 6-71. switching characteristics over recommended operating conditions for uartx transmit (1) (see figure 6-40 ) 1.2v, 1.1v, 1.0v no. parameter unit min max 1 f (baud) maximum programmable baud rate d/e (2) (3) mbaud (4) 2 t w(utxdb) pulse duration, transmit data bit (txdn) u - 2 u + 2 ns 3 t w(utxsb) pulse duration, transmit start bit u - 2 u + 2 ns (1) u = uart baud time = 1/programmed baud rate. (2) d = uart input clock in mhz. for uart0, the uart input clock is sysclk2. for uart1 or uart2, the uart input clock is async3 (either pll0_syclk2 or pll1_sysclk2). (3) e = uart divisor x uart sampling rate. the uart divisor is set through the uart divisor latch registers (dll and dlh). the uart sampling rate is set through the over-sampling mode select bit (osm_sel) of the uart mode definition register (mdr). (4) baud rate is not indicative of data rate. actual data rate will be limited by system factors such as edma loading, emif/ddr loading, system frequency, etc. figure 6-40. uart transmit/receive timing 140 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 3 2 start bit data bits uart_txdn uart_rxdn 5 data bits bit start 4
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.18 universal serial bus otg controller (usb0) [usb2.0 otg] the usb2.0 peripheral supports the following features: ? usb 2.0 peripheral at speeds high speed (hs: 480 mb/s) and full speed (fs: 12 mb/s) ? usb 2.0 host at speeds hs, fs, and low speed (ls: 1.5 mb/s) ? all transfer modes (control, bulk, interrupt, and isochronous) ? 4 transmit (tx) and 4 receive (rx) endpoints in addition to endpoint 0 ? fifo ram ? 4k endpoint ? programmable size ? integrated usb 2.0 high speed phy ? connects to a standard charge pump for vbus 5 v generation ? rndis mode for accelerating rndis type protocols using short packet termination over usb important notice: the usb0 controller module clock (pll0_sysclk2) must be greater than 30 mhz for proper operation of the usb controller. a clock rate of 60 mhz or greater is recommended to avoid data throughput reduction. table 6-72 is the list of usb otg registers. table 6-72. universal serial bus otg (usb0) registers byte address acronym register description 0x01e0 0000 revid revision register 0x01e0 0004 ctrlr control register 0x01e0 0008 statr status register 0x01e0 000c emur emulation register 0x01e0 0010 mode mode register 0x01e0 0014 autoreq autorequest register 0x01e0 0018 srpfixtime srp fix time register 0x01e0 001c teardown teardown register 0x01e0 0020 intsrcr usb interrupt source register 0x01e0 0024 intsetr usb interrupt source set register 0x01e0 0028 intclrr usb interrupt source clear register 0x01e0 002c intmskr usb interrupt mask register 0x01e0 0030 intmsksetr usb interrupt mask set register 0x01e0 0034 intmskclrr usb interrupt mask clear register 0x01e0 0038 intmaskedr usb interrupt source masked register 0x01e0 003c eoir usb end of interrupt register 0x01e0 0040 - reserved 0x01e0 0050 genrndissz1 generic rndis size ep1 0x01e0 0054 genrndissz2 generic rndis size ep2 0x01e0 0058 genrndissz3 generic rndis size ep3 0x01e0 005c genrndissz4 generic rndis size ep4 0x01e0 0400 faddr function address register 0x01e0 0401 power power management register 0x01e0 0402 intrtx interrupt register for endpoint 0 plus transmit endpoints 1 to 4 0x01e0 0404 intrrx interrupt register for receive endpoints 1 to 4 0x01e0 0406 intrtxe interrupt enable register for intrtx 0x01e0 0408 intrrxe interrupt enable register for intrrx 0x01e0 040a intrusb interrupt register for common usb interrupts 0x01e0 040b intrusbe interrupt enable register for intrusb copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 141 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-72. universal serial bus otg (usb0) registers (continued) byte address acronym register description 0x01e0 040c frame frame number register 0x01e0 040e index index register for selecting the endpoint status and control registers 0x01e0 040f testmode register to enable the usb 2.0 test modes indexed registers these registers operate on the endpoint selected by the index register 0x01e0 0410 txmaxp maximum packet size for peripheral/host transmit endpoint (index register set to select endpoints 1-4 only) 0x01e0 0412 peri_csr0 control status register for endpoint 0 in peripheral mode. (index register set to select endpoint 0) host_csr0 control status register for endpoint 0 in host mode. (index register set to select endpoint 0) peri_txcsr control status register for peripheral transmit endpoint. (index register set to select endpoints 1-4) host_txcsr control status register for host transmit endpoint. (index register set to select endpoints 1-4) 0x01e0 0414 rxmaxp maximum packet size for peripheral/host receive endpoint (index register set to select endpoints 1-4 only) 0x01e0 0416 peri_rxcsr control status register for peripheral receive endpoint. (index register set to select endpoints 1-4) host_rxcsr control status register for host receive endpoint. (index register set to select endpoints 1-4) 0x01e0 0418 count0 number of received bytes in endpoint 0 fifo. (index register set to select endpoint 0) rxcount number of bytes in host receive endpoint fifo. (index register set to select endpoints 1- 4) 0x01e0 041a host_type0 defines the speed of endpoint 0 host_txtype sets the operating speed, transaction protocol and peripheral endpoint number for the host transmit endpoint. (index register set to select endpoints 1-4 only) 0x01e0 041b host_naklimit0 sets the nak response timeout on endpoint 0. (index register set to select endpoint 0) host_txinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host transmit endpoint. (index register set to select endpoints 1-4 only) 0x01e0 041c host_rxtype sets the operating speed, transaction protocol and peripheral endpoint number for the host receive endpoint. (index register set to select endpoints 1-4 only) 0x01e0 041d host_rxinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host receive endpoint. (index register set to select endpoints 1-4 only) 0x01e0 041f configdata returns details of core configuration. (index register set to select endpoint 0) fifo 0x01e0 0420 fifo0 transmit and receive fifo register for endpoint 0 0x01e0 0424 fifo1 transmit and receive fifo register for endpoint 1 0x01e0 0428 fifo2 transmit and receive fifo register for endpoint 2 0x01e0 042c fifo3 transmit and receive fifo register for endpoint 3 0x01e0 0430 fifo4 transmit and receive fifo register for endpoint 4 otg device control 0x01e0 0460 devctl device control register dynamic fifo control 0x01e0 0462 txfifosz transmit endpoint fifo size (index register set to select endpoints 1-4 only) 0x01e0 0463 rxfifosz receive endpoint fifo size (index register set to select endpoints 1-4 only) 142 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-72. universal serial bus otg (usb0) registers (continued) byte address acronym register description 0x01e0 0464 txfifoaddr transmit endpoint fifo address (index register set to select endpoints 1-4 only) 0x01e0 0466 rxfifoaddr receive endpoint fifo address (index register set to select endpoints 1-4 only) 0x01e0 046c hwvers hardware version register target endpoint 0 control registers, valid only in host mode 0x01e0 0480 txfuncaddr address of the target function that has to be accessed through the associated transmit endpoint. 0x01e0 0482 txhubaddr address of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 0483 txhubport port of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 0484 rxfuncaddr address of the target function that has to be accessed through the associated receive endpoint. 0x01e0 0486 rxhubaddr address of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 0487 rxhubport port of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. target endpoint 1 control registers, valid only in host mode 0x01e0 0488 txfuncaddr address of the target function that has to be accessed through the associated transmit endpoint. 0x01e0 048a txhubaddr address of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 048b txhubport port of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 048c rxfuncaddr address of the target function that has to be accessed through the associated receive endpoint. 0x01e0 048e rxhubaddr address of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 048f rxhubport port of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. target endpoint 2 control registers, valid only in host mode 0x01e0 0490 txfuncaddr address of the target function that has to be accessed through the associated transmit endpoint. 0x01e0 0492 txhubaddr address of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 0493 txhubport port of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 0494 rxfuncaddr address of the target function that has to be accessed through the associated receive endpoint. 0x01e0 0496 rxhubaddr address of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 0497 rxhubport port of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. target endpoint 3 control registers, valid only in host mode 0x01e0 0498 txfuncaddr address of the target function that has to be accessed through the associated transmit endpoint. 0x01e0 049a txhubaddr address of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 049b txhubport port of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 049c rxfuncaddr address of the target function that has to be accessed through the associated receive endpoint. 0x01e0 049e rxhubaddr address of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 143 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-72. universal serial bus otg (usb0) registers (continued) byte address acronym register description 0x01e0 049f rxhubport port of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. target endpoint 4 control registers, valid only in host mode 0x01e0 04a0 txfuncaddr address of the target function that has to be accessed through the associated transmit endpoint. 0x01e0 04a2 txhubaddr address of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 04a3 txhubport port of the hub that has to be accessed through the associated transmit endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 04a4 rxfuncaddr address of the target function that has to be accessed through the associated receive endpoint. 0x01e0 04a6 rxhubaddr address of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. 0x01e0 04a7 rxhubport port of the hub that has to be accessed through the associated receive endpoint. this is used only when full speed or low speed device is connected via a usb2.0 high-speed hub. control and status register for endpoint 0 0x01e0 0502 peri_csr0 control status register for endpoint 0 in peripheral mode host_csr0 control status register for endpoint 0 in host mode 0x01e0 0508 count0 number of received bytes in endpoint 0 fifo 0x01e0 050a host_type0 defines the speed of endpoint 0 0x01e0 050b host_naklimit0 sets the nak response timeout on endpoint 0 0x01e0 050f configdata returns details of core configuration. control and status register for endpoint 1 0x01e0 0510 txmaxp maximum packet size for peripheral/host transmit endpoint 0x01e0 0512 peri_txcsr control status register for peripheral transmit endpoint (peripheral mode) host_txcsr control status register for host transmit endpoint (host mode) 0x01e0 0514 rxmaxp maximum packet size for peripheral/host receive endpoint 0x01e0 0516 peri_rxcsr control status register for peripheral receive endpoint (peripheral mode) host_rxcsr control status register for host receive endpoint (host mode) 0x01e0 0518 rxcount number of bytes in host receive endpoint fifo 0x01e0 051a host_txtype sets the operating speed, transaction protocol and peripheral endpoint number for the host transmit endpoint. 0x01e0 051b host_txinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host transmit endpoint. 0x01e0 051c host_rxtype sets the operating speed, transaction protocol and peripheral endpoint number for the host receive endpoint. 0x01e0 051d host_rxinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host receive endpoint. control and status register for endpoint 2 0x01e0 0520 txmaxp maximum packet size for peripheral/host transmit endpoint 0x01e0 0522 peri_txcsr control status register for peripheral transmit endpoint (peripheral mode) host_txcsr control status register for host transmit endpoint (host mode) 0x01e0 0524 rxmaxp maximum packet size for peripheral/host receive endpoint 0x01e0 0526 peri_rxcsr control status register for peripheral receive endpoint (peripheral mode) host_rxcsr control status register for host receive endpoint (host mode) 0x01e0 0528 rxcount number of bytes in host receive endpoint fifo 0x01e0 052a host_txtype sets the operating speed, transaction protocol and peripheral endpoint number for the host transmit endpoint. 0x01e0 052b host_txinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host transmit endpoint. 0x01e0 052c host_rxtype sets the operating speed, transaction protocol and peripheral endpoint number for the host receive endpoint. 144 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-72. universal serial bus otg (usb0) registers (continued) byte address acronym register description 0x01e0 052d host_rxinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host receive endpoint. control and status register for endpoint 3 0x01e0 0530 txmaxp maximum packet size for peripheral/host transmit endpoint 0x01e0 0532 peri_txcsr control status register for peripheral transmit endpoint (peripheral mode) host_txcsr control status register for host transmit endpoint (host mode) 0x01e0 0534 rxmaxp maximum packet size for peripheral/host receive endpoint 0x01e0 0536 peri_rxcsr control status register for peripheral receive endpoint (peripheral mode) host_rxcsr control status register for host receive endpoint (host mode) 0x01e0 0538 rxcount number of bytes in host receive endpoint fifo 0x01e0 053a host_txtype sets the operating speed, transaction protocol and peripheral endpoint number for the host transmit endpoint. 0x01e0 053b host_txinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host transmit endpoint. 0x01e0 053c host_rxtype sets the operating speed, transaction protocol and peripheral endpoint number for the host receive endpoint. 0x01e0 053d host_rxinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host receive endpoint. control and status register for endpoint 4 0x01e0 0540 txmaxp maximum packet size for peripheral/host transmit endpoint 0x01e0 0542 peri_txcsr control status register for peripheral transmit endpoint (peripheral mode) host_txcsr control status register for host transmit endpoint (host mode) 0x01e0 0544 rxmaxp maximum packet size for peripheral/host receive endpoint 0x01e0 0546 peri_rxcsr control status register for peripheral receive endpoint (peripheral mode) host_rxcsr control status register for host receive endpoint (host mode) 0x01e0 0548 rxcount number of bytes in host receive endpoint fifo 0x01e0 054a host_txtype sets the operating speed, transaction protocol and peripheral endpoint number for the host transmit endpoint. 0x01e0 054b host_txinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host transmit endpoint. 0x01e0 054c host_rxtype sets the operating speed, transaction protocol and peripheral endpoint number for the host receive endpoint. 0x01e0 054d host_rxinterval sets the polling interval for interrupt/isoc transactions or the nak response timeout on bulk transactions for host receive endpoint. dma registers 0x01e0 1000 dmarevid dma revision register 0x01e0 1004 tdfdq dma teardown free descriptor queue control register 0x01e0 1008 dmaemu dma emulation control register 0x01e0 1800 txgcr[0] transmit channel 0 global configuration register 0x01e0 1808 rxgcr[0] receive channel 0 global configuration register 0x01e0 180c rxhpcra[0] receive channel 0 host packet configuration register a 0x01e0 1810 rxhpcrb[0] receive channel 0 host packet configuration register b 0x01e0 1820 txgcr[1] transmit channel 1 global configuration register 0x01e0 1828 rxgcr[1] receive channel 1 global configuration register 0x01e0 182c rxhpcra[1] receive channel 1 host packet configuration register a 0x01e0 1830 rxhpcrb[1] receive channel 1 host packet configuration register b 0x01e0 1840 txgcr[2] transmit channel 2 global configuration register 0x01e0 1848 rxgcr[2] receive channel 2 global configuration register 0x01e0 184c rxhpcra[2] receive channel 2 host packet configuration register a 0x01e0 1850 rxhpcrb[2] receive channel 2 host packet configuration register b copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 145 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-72. universal serial bus otg (usb0) registers (continued) byte address acronym register description 0x01e0 1860 txgcr[3] transmit channel 3 global configuration register 0x01e0 1868 rxgcr[3] receive channel 3 global configuration register 0x01e0 186c rxhpcra[3] receive channel 3 host packet configuration register a 0x01e0 1870 rxhpcrb[3] receive channel 3 host packet configuration register b 0x01e0 2000 dma_sched_ctrl dma scheduler control register 0x01e0 2800 word[0] dma scheduler table word 0 0x01e0 2804 word[1] dma scheduler table word 1 . . . . . . . . . 0x01e0 28fc word[63] dma scheduler table word 63 queue manager registers 0x01e0 4000 qmgrrevid queue manager revision register 0x01e0 4008 diversion queue diversion register 0x01e0 4020 fdbsc0 free descriptor/buffer starvation count register 0 0x01e0 4024 fdbsc1 free descriptor/buffer starvation count register 1 0x01e0 4028 fdbsc2 free descriptor/buffer starvation count register 2 0x01e0 402c fdbsc3 free descriptor/buffer starvation count register 3 0x01e0 4080 lram0base linking ram region 0 base address register 0x01e0 4084 lram0size linking ram region 0 size register 0x01e0 4088 lram1base linking ram region 1 base address register 0x01e0 4090 pend0 queue pending register 0 0x01e0 4094 pend1 queue pending register 1 0x01e0 5000 qmemrbase[0] memory region 0 base address register 0x01e0 5004 qmemrctrl[0] memory region 0 control register 0x01e0 5010 qmemrbase[1] memory region 1 base address register 0x01e0 5014 qmemrctrl[1] memory region 1 control register . . . . . . . . . 0x01e0 50f0 qmemrbase[15] memory region 15 base address register 0x01e0 50f4 qmemrctrl[15] memory region 15 control register 0x01e0 600c ctrld[0] queue manager queue 0 control register d 0x01e0 601c ctrld[1] queue manager queue 1 control register d . . . . . . . . . 0x01e0 63fc ctrld[63] queue manager queue 63 status register d 0x01e0 6800 qstata[0] queue manager queue 0 status register a 0x01e0 6804 qstatb[0] queue manager queue 0 status register b 0x01e0 6808 qstatc[0] queue manager queue 0 status register c 0x01e0 6810 qstata[1] queue manager queue 1 status register a 0x01e0 6814 qstatb[1] queue manager queue 1 status register b 0x01e0 6818 qstatc[1] queue manager queue 1 status register c . . . . . . . . . 0x01e0 6bf0 qstata[63] queue manager queue 63 status register a 0x01e0 6bf4 qstatb[63] queue manager queue 63 status register b 0x01e0 6bf8 qstatc[63] queue manager queue 63 status register c 146 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.18.1 usb0 [usb2.0] electrical data/timing the usb phy pll can support input clock of the following frequencies: 12.0 mhz, 13.0 mhz, 19.2 mhz, 20.0 mhz, 24.0 mhz, 26.0 mhz, 38.4 mhz, 40.0 mhz or 48.0 mhz. usb_refclkin jitter tolerance is 50 ppm maximum. table 6-73. switching characteristics over recommended operating conditions for usb0 [usb2.0] (see figure 6-41 ) 1.2v, 1.1v, 1.0v low speed full speed high speed no. parameter unit 1.5 mbps 12 mbps 480 mbps min max min max min max 1 t r(d) rise time, usb_dp and usb_dm signals (1) 75 300 4 20 0.5 ns 2 t f(d) fall time, usb_dp and usb_dm signals (1) 75 300 4 20 0.5 ns 3 t rfm rise/fall time, matching (2) 80 120 90 111 - - % 4 v crs output signal cross-over voltage (1) 1.3 2 1.3 2 - - v 5 t jr(source)nt source (host) driver jitter, next transition 2 2 (3) ns t jr(func)nt function driver jitter, next transition 25 2 (3) ns 6 t jr(source)pt source (host) driver jitter, paired transition (4) 1 1 (3) ns t jr(func)pt function driver jitter, paired transition 10 1 (3) ns 7 t w(eopt) pulse duration, eop transmitter 1250 1500 160 175 - - ns 8 t w(eopr) pulse duration, eop receiver 670 82 - ns 9 t (drate) data rate 1.5 12 480 mb/s 10 z drv driver output resistance - - 40.5 49.5 40.5 49.5 ? 11 z inp receiver input impedance 100k 100k - - ? (1) low speed: c l = 200 pf, full speed: c l = 50 pf, high speed: c l = 50 pf (2) t rfm = (t r /t f ) x 100. [excluding the first transaction from the idle state.] (3) for more detailed information, see the universal serial bus specification revision 2.0, chapter 7. electrical. (4) t jr = t px(1) - t px(0) figure 6-41. usb2.0 integrated transceiver interface timing copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 147 submit documentation feedback product folder links: am1802 t r t f v crs 90% v oh 10% v ol usb_dm usb_dp t per ? t jr
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.19 ethernet media access controller (emac) the ethernet media access controller (emac) provides an efficient interface between device and the network. the emac supports both 10base-t and 100base-tx, or 10 mbits/second (mbps) and 100 mbps in either half- or full-duplex mode, with hardware flow control and quality of service (qos) support. the emac controls the flow of packet data from the device to the phy. the mdio module controls phy configuration and status monitoring. both the emac and the mdio modules interface to the device through a custom interface that allows efficient data transmission and reception. this custom interface is referred to as the emac control module, and is considered integral to the emac/mdio peripheral. the control module is also used to multiplex and control interrupts. 6.19.1 emac peripheral register description(s) table 6-74. ethernet media access controller (emac) registers byte address acronym register description 0x01e2 3000 txrev transmit revision register 0x01e2 3004 txcontrol transmit control register 0x01e2 3008 txteardown transmit teardown register 0x01e2 3010 rxrev receive revision register 0x01e2 3014 rxcontrol receive control register 0x01e2 3018 rxteardown receive teardown register 0x01e2 3080 txintstatraw transmit interrupt status (unmasked) register 0x01e2 3084 txintstatmasked transmit interrupt status (masked) register 0x01e2 3088 txintmaskset transmit interrupt mask set register 0x01e2 308c txintmaskclear transmit interrupt clear register 0x01e2 3090 macinvector mac input vector register 0x01e2 3094 maceoivector mac end of interrupt vector register 0x01e2 30a0 rxintstatraw receive interrupt status (unmasked) register 0x01e2 30a4 rxintstatmasked receive interrupt status (masked) register 0x01e2 30a8 rxintmaskset receive interrupt mask set register 0x01e2 30ac rxintmaskclear receive interrupt mask clear register 0x01e2 30b0 macintstatraw mac interrupt status (unmasked) register 0x01e2 30b4 macintstatmasked mac interrupt status (masked) register 0x01e2 30b8 macintmaskset mac interrupt mask set register 0x01e2 30bc macintmaskclear mac interrupt mask clear register 0x01e2 3100 rxmbpenable receive multicast/broadcast/promiscuous channel enable register 0x01e2 3104 rxunicastset receive unicast enable set register 0x01e2 3108 rxunicastclear receive unicast clear register 0x01e2 310c rxmaxlen receive maximum length register 0x01e2 3110 rxbufferoffset receive buffer offset register 0x01e2 3114 rxfilterlowthresh receive filter low priority frame threshold register 0x01e2 3120 rx0flowthresh receive channel 0 flow control threshold register 0x01e2 3124 rx1flowthresh receive channel 1 flow control threshold register 0x01e2 3128 rx2flowthresh receive channel 2 flow control threshold register 0x01e2 312c rx3flowthresh receive channel 3 flow control threshold register 0x01e2 3130 rx4flowthresh receive channel 4 flow control threshold register 0x01e2 3134 rx5flowthresh receive channel 5 flow control threshold register 0x01e2 3138 rx6flowthresh receive channel 6 flow control threshold register 0x01e2 313c rx7flowthresh receive channel 7 flow control threshold register 148 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-74. ethernet media access controller (emac) registers (continued) byte address acronym register description 0x01e2 3140 rx0freebuffer receive channel 0 free buffer count register 0x01e2 3144 rx1freebuffer receive channel 1 free buffer count register 0x01e2 3148 rx2freebuffer receive channel 2 free buffer count register 0x01e2 314c rx3freebuffer receive channel 3 free buffer count register 0x01e2 3150 rx4freebuffer receive channel 4 free buffer count register 0x01e2 3154 rx5freebuffer receive channel 5 free buffer count register 0x01e2 3158 rx6freebuffer receive channel 6 free buffer count register 0x01e2 315c rx7freebuffer receive channel 7 free buffer count register 0x01e2 3160 maccontrol mac control register 0x01e2 3164 macstatus mac status register 0x01e2 3168 emcontrol emulation control register 0x01e2 316c fifocontrol fifo control register 0x01e2 3170 macconfig mac configuration register 0x01e2 3174 softreset soft reset register 0x01e2 31d0 macsrcaddrlo mac source address low bytes register 0x01e2 31d4 macsrcaddrhi mac source address high bytes register 0x01e2 31d8 machash1 mac hash address register 1 0x01e2 31dc machash2 mac hash address register 2 0x01e2 31e0 bofftest back off test register 0x01e2 31e4 tpacetest transmit pacing algorithm test register 0x01e2 31e8 rxpause receive pause timer register 0x01e2 31ec txpause transmit pause timer register 0x01e2 3200 - 0x01e2 32fc (see table 6-75 ) emac statistics registers 0x01e2 3500 macaddrlo mac address low bytes register, used in receive address matching 0x01e2 3504 macaddrhi mac address high bytes register, used in receive address matching 0x01e2 3508 macindex mac index register 0x01e2 3600 tx0hdp transmit channel 0 dma head descriptor pointer register 0x01e2 3604 tx1hdp transmit channel 1 dma head descriptor pointer register 0x01e2 3608 tx2hdp transmit channel 2 dma head descriptor pointer register 0x01e2 360c tx3hdp transmit channel 3 dma head descriptor pointer register 0x01e2 3610 tx4hdp transmit channel 4 dma head descriptor pointer register 0x01e2 3614 tx5hdp transmit channel 5 dma head descriptor pointer register 0x01e2 3618 tx6hdp transmit channel 6 dma head descriptor pointer register 0x01e2 361c tx7hdp transmit channel 7 dma head descriptor pointer register 0x01e2 3620 rx0hdp receive channel 0 dma head descriptor pointer register 0x01e2 3624 rx1hdp receive channel 1 dma head descriptor pointer register 0x01e2 3628 rx2hdp receive channel 2 dma head descriptor pointer register 0x01e2 362c rx3hdp receive channel 3 dma head descriptor pointer register 0x01e2 3630 rx4hdp receive channel 4 dma head descriptor pointer register 0x01e2 3634 rx5hdp receive channel 5 dma head descriptor pointer register 0x01e2 3638 rx6hdp receive channel 6 dma head descriptor pointer register 0x01e2 363c rx7hdp receive channel 7 dma head descriptor pointer register 0x01e2 3640 tx0cp transmit channel 0 completion pointer register 0x01e2 3644 tx1cp transmit channel 1 completion pointer register 0x01e2 3648 tx2cp transmit channel 2 completion pointer register 0x01e2 364c tx3cp transmit channel 3 completion pointer register 0x01e2 3650 tx4cp transmit channel 4 completion pointer register copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 149 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-74. ethernet media access controller (emac) registers (continued) byte address acronym register description 0x01e2 3654 tx5cp transmit channel 5 completion pointer register 0x01e2 3658 tx6cp transmit channel 6 completion pointer register 0x01e2 365c tx7cp transmit channel 7 completion pointer register 0x01e2 3660 rx0cp receive channel 0 completion pointer register 0x01e2 3664 rx1cp receive channel 1 completion pointer register 0x01e2 3668 rx2cp receive channel 2 completion pointer register 0x01e2 366c rx3cp receive channel 3 completion pointer register 0x01e2 3670 rx4cp receive channel 4 completion pointer register 0x01e2 3674 rx5cp receive channel 5 completion pointer register 0x01e2 3678 rx6cp receive channel 6 completion pointer register 0x01e2 367c rx7cp receive channel 7 completion pointer register table 6-75. emac statistics registers byte address acronym register description 0x01e2 3200 rxgoodframes good receive frames register broadcast receive frames register 0x01e2 3204 rxbcastframes (total number of good broadcast frames received) multicast receive frames register 0x01e2 3208 rxmcastframes (total number of good multicast frames received) 0x01e2 320c rxpauseframes pause receive frames register receive crc errors register (total number of frames received with 0x01e2 3210 rxcrcerrors crc errors) receive alignment/code errors register 0x01e2 3214 rxaligncodeerrors (total number of frames received with alignment/code errors) receive oversized frames register 0x01e2 3218 rxoversized (total number of oversized frames received) receive jabber frames register 0x01e2 321c rxjabber (total number of jabber frames received) receive undersized frames register 0x01e2 3220 rxundersized (total number of undersized frames received) 0x01e2 3224 rxfragments receive frame fragments register 0x01e2 3228 rxfiltered filtered receive frames register 0x01e2 322c rxqosfiltered received qos filtered frames register receive octet frames register 0x01e2 3230 rxoctets (total number of received bytes in good frames) good transmit frames register 0x01e2 3234 txgoodframes (total number of good frames transmitted) 0x01e2 3238 txbcastframes broadcast transmit frames register 0x01e2 323c txmcastframes multicast transmit frames register 0x01e2 3240 txpauseframes pause transmit frames register 0x01e2 3244 txdeferred deferred transmit frames register 0x01e2 3248 txcollision transmit collision frames register 0x01e2 324c txsinglecoll transmit single collision frames register 0x01e2 3250 txmulticoll transmit multiple collision frames register 0x01e2 3254 txexcessivecoll transmit excessive collision frames register 0x01e2 3258 txlatecoll transmit late collision frames register 0x01e2 325c txunderrun transmit underrun error register 0x01e2 3260 txcarriersense transmit carrier sense errors register 0x01e2 3264 txoctets transmit octet frames register 0x01e2 3268 frame64 transmit and receive 64 octet frames register 150 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-75. emac statistics registers (continued) byte address acronym register description 0x01e2 326c frame65t127 transmit and receive 65 to 127 octet frames register 0x01e2 3270 frame128t255 transmit and receive 128 to 255 octet frames register 0x01e2 3274 frame256t511 transmit and receive 256 to 511 octet frames register 0x01e2 3278 frame512t1023 transmit and receive 512 to 1023 octet frames register 0x01e2 327c frame1024tup transmit and receive 1024 to 1518 octet frames register 0x01e2 3280 netoctets network octet frames register 0x01e2 3284 rxsofoverruns receive fifo or dma start of frame overruns register 0x01e2 3288 rxmofoverruns receive fifo or dma middle of frame overruns register 0x01e2 328c rxdmaoverruns receive dma start of frame and middle of frame overruns register table 6-76. emac control module registers byte address acronym register description 0x01e2 2000 rev emac control module revision register 0x01e2 2004 softreset emac control module software reset register 0x01e2 200c intcontrol emac control module interrupt control register 0x01e2 2010 c0rxthreshen emac control module interrupt core 0 receive threshold interrupt enable register 0x01e2 2014 c0rxen emac control module interrupt core 0 receive interrupt enable register 0x01e2 2018 c0txen emac control module interrupt core 0 transmit interrupt enable register 0x01e2 201c c0miscen emac control module interrupt core 0 miscellaneous interrupt enable register 0x01e2 2020 c1rxthreshen emac control module interrupt core 1 receive threshold interrupt enable register 0x01e2 2024 c1rxen emac control module interrupt core 1 receive interrupt enable register 0x01e2 2028 c1txen emac control module interrupt core 1 transmit interrupt enable register 0x01e2 202c c1miscen emac control module interrupt core 1 miscellaneous interrupt enable register 0x01e2 2030 c2rxthreshen emac control module interrupt core 2 receive threshold interrupt enable register 0x01e2 2034 c2rxen emac control module interrupt core 2 receive interrupt enable register 0x01e2 2038 c2txen emac control module interrupt core 2 transmit interrupt enable register 0x01e2 203c c2miscen emac control module interrupt core 2 miscellaneous interrupt enable register 0x01e2 2040 c0rxthreshstat emac control module interrupt core 0 receive threshold interrupt status register 0x01e2 2044 c0rxstat emac control module interrupt core 0 receive interrupt status register 0x01e2 2048 c0txstat emac control module interrupt core 0 transmit interrupt status register 0x01e2 204c c0miscstat emac control module interrupt core 0 miscellaneous interrupt status register 0x01e2 2050 c1rxthreshstat emac control module interrupt core 1 receive threshold interrupt status register 0x01e2 2054 c1rxstat emac control module interrupt core 1 receive interrupt status register 0x01e2 2058 c1txstat emac control module interrupt core 1 transmit interrupt status register 0x01e2 205c c1miscstat emac control module interrupt core 1 miscellaneous interrupt status register 0x01e2 2060 c2rxthreshstat emac control module interrupt core 2 receive threshold interrupt status register 0x01e2 2064 c2rxstat emac control module interrupt core 2 receive interrupt status register 0x01e2 2068 c2txstat emac control module interrupt core 2 transmit interrupt status register 0x01e2 206c c2miscstat emac control module interrupt core 2 miscellaneous interrupt status register 0x01e2 2070 c0rximax emac control module interrupt core 0 receive interrupts per millisecond register 0x01e2 2074 c0tximax emac control module interrupt core 0 transmit interrupts per millisecond register 0x01e2 2078 c1rximax emac control module interrupt core 1 receive interrupts per millisecond register 0x01e2 207c c1tximax emac control module interrupt core 1 transmit interrupts per millisecond register 0x01e2 2080 c2rximax emac control module interrupt core 2 receive interrupts per millisecond register 0x01e2 2084 c2tximax emac control module interrupt core 2 transmit interrupts per millisecond register copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 151 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-77. emac control module ram byte address description 0x01e2 0000 - 0x01e2 1fff emac local buffer descriptor memory 6.19.1.1 emac electrical data/timing table 6-78. timing requirements for mii_rxclk (see figure 6-42 ) 1.2v, 1.1v 1.0v no. 10 mbps 100 mbps 10 mbps unit min max min max min max 1 t c(mii_rxclk) cycle time, mii_rxclk 400 40 400 ns 2 t w(mii_rxclkh) pulse duration, mii_rxclk high 140 14 140 ns 3 t w(mii_rxclkl) pulse duration, mii_rxclk low 140 14 140 ns figure 6-42. mii_rxclk timing (emac - receive) table 6-79. timing requirements for mii_txclk (see figure 6-43 ) 1.2v, 1.1v 1.0v no. 10 mbps 100 mbps 10 mbps unit min max min max min max 1 t c(mii_txclk) cycle time, mii_txclk 400 40 400 ns 2 t w(mii_txclkh) pulse duration, mii_txclk high 140 14 140 ns 3 t w(mii_txclkl) pulse duration, mii_txclk low 140 14 140 ns figure 6-43. mii_txclk timing (emac - transmit) 152 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 mii_txclk 2 3 1 mii_rxclk 2 3 1
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-80. timing requirements for emac mii receive 10/100 mbit/s (1) (see figure 6-44 ) 1.2v, 1.1v, 1.0v no. unit min max 1 t su(mrxd-mii_rxclkh) setup time, receive selected signals valid before mii_rxclk high 8 ns 2 t h(mii_rxclkh-mrxd) hold time, receive selected signals valid after mii_rxclk high 8 ns (1) receive selected signals include: mii_rxd[3]-mii_rxd[0], mii_rxdv, and mii_rxer. figure 6-44. emac receive interface timing table 6-81. switching characteristics over recommended operating conditions for emac mii transmit 10/100 mbit/s (1) (see figure 6-45 ) 1.2v, 1.1v 1.0v no. parameter unit min max min max t d(mii_txclkh- 1 delay time, mii_txclk high to transmit selected signals valid 2 25 2 32 ns mtxd) (1) transmit selected signals include: mtxd3-mtxd0, and mii_txen. figure 6-45. emac transmit interface timing copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 153 submit documentation feedback product folder links: am1802 1 mii_tclk (input) mii_txd[3]-mii_txd[0], mii_txen (outputs) mii_rxclk (input) 1 2 mii_rxd[3]-mii_rxd[0], mii_rxdv, mii_rxer (inputs)
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-82. timing requirements for emac rmii 1.2v, 1.1v (1) no. unit min typ max 1 tc(refclk) cycle time, rmii_mhz_50_clk (2) 20 ns 2 tw(refclkh) pulse width, rmii_mhz_50_clk high 7 13 ns 3 tw(refclkl) pulse width, rmii_mhz_50_clk low 7 13 ns 6 tsu(rxd-refclk) input setup time, rxd valid before rmii_mhz_50_clk high 4 ns 7 th(refclk-rxd) input hold time, rxd valid after rmii_mhz_50_clk high 2 ns 8 tsu(crsdv-refclk) input setup time, crsdv valid before rmii_mhz_50_clk high 4 ns 9 th(refclk-crsdv) input hold time, crsdv valid after rmii_mhz_50_clk high 2 ns 10 tsu(rxer-refclk) input setup time, rxer valid before rmii_mhz_50_clk high 4 ns 11 th(refclkr-rxer) input hold time, rxer valid after rmii_mhz_50_clk high 2 ns (1) rmii is not supported at operating points below 1.1v nominal. (2) per the rmii industry specification, the rmii reference clock (rmii_mhz_50_clk) must have jitter tolerance of 50 ppm or less. table 6-83. switching characteristics over recommended operating conditions for emac rmii 1.2v, 1.1v (1) no. parameter unit min typ max 4 td(refclk-txd) output delay time, rmii_mhz_50_clk high to txd valid 2.5 13 ns 5 td(refclk-txen) output delay time, rmii_mhz_50_clk high to txen valid 2.5 13 ns (1) rmii is not supported at operating points below 1.1v nominal. figure 6-46. rmii timing diagram 154 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 rmii_mhz_50_clk rmii_txen rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv rmii_rxer 1 2 3 5 5 4 6 7 8 9 10 11
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.20 management data input/output (mdio) the management data input/output (mdio) module continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system. the management data input/output (mdio) module implements the 802.3 serial management interface to interrogate and control ethernet phy(s) using a shared two-wire bus. host software uses the mdio module to configure the auto-negotiation parameters of each phy attached to the emac, retrieve the negotiation results, and configure required parameters in the emac module for correct operation. the module is designed to allow almost transparent operation of the mdio interface, with very little maintenance from the core processor. only one phy may be connected at any given time. 6.20.1 mdio registers for a list of supported mdio registers see table 6-84 [mdio registers]. table 6-84. mdio register memory map byte address acronym register name 0x01e2 4000 rev revision identification register 0x01e2 4004 control mdio control register 0x01e2 4008 alive mdio phy alive status register 0x01e2 400c link mdio phy link status register 0x01e2 4010 linkintraw mdio link status change interrupt (unmasked) register 0x01e2 4014 linkintmasked mdio link status change interrupt (masked) register 0x01e2 4018 - reserved 0x01e2 4020 userintraw mdio user command complete interrupt (unmasked) register 0x01e2 4024 userintmasked mdio user command complete interrupt (masked) register 0x01e2 4028 userintmaskset mdio user command complete interrupt mask set register 0x01e2 402c userintmaskclear mdio user command complete interrupt mask clear register 0x01e2 4030 - 0x01e2 407c - reserved 0x01e2 4080 useraccess0 mdio user access register 0 0x01e2 4084 userphysel0 mdio user phy select register 0 0x01e2 4088 useraccess1 mdio user access register 1 0x01e2 408c userphysel1 mdio user phy select register 1 0x01e2 4090 - 0x01e2 47ff - reserved copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 155 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.20.2 management data input/output (mdio) electrical data/timing table 6-85. timing requirements for mdio input (see figure 6-47 and figure 6-48 ) 1.3v, 1.2v, 1.1v 1.0v no. unit min max min max 1 t c(mdclk) cycle time, mdclk 400 400 ns 2 t w(mdclk) pulse duration, mdclk high/low 180 180 ns 3 t t(mdclk) transition time, mdclk 5 5 ns 4 t su(mdio-mdclkh) setup time, mdio data input valid before mdclk high 16 21 ns 5 t h(mdclkh-mdio) hold time, mdio data input valid after mdclk high 0 0 ns figure 6-47. mdio input timing table 6-86. switching characteristics over recommended operating conditions for mdio output (see figure 6-48 ) 1.1v, 1.0v no. unit min max 7 t d(mdclkl-mdio) delay time, mdclk low to mdio data output valid 0 100 ns figure 6-48. mdio output timing 156 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 1 7 mdclk mdio (output) 1 4 5 mdclk mdio (input) 3 3
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.21 timers the timers support the following features: ? configurable as single 64-bit timer or two 32-bit timers ? period timeouts generate interrupts, dma events or external pin events ? 8 32-bit compare registers ? compare matches generate interrupt events ? capture capability ? 64-bit watchdog capability (timer64p1 only) table 6-87 lists the timer registers. table 6-87. timer registers timer64p 0 timer64p 1 timer64p 2 timer64p 3 byte byte acronym register description byte address byte address address address 0x01c2 0000 0x01c2 1000 0x01f0 c000 0x01f0 d000 rev revision register 0x01c2 0004 0x01c2 1004 0x01f0 c004 0x01f0 d004 emumgt emulation management register 0x01c2 0008 0x01c2 1008 0x01f0 c008 0x01f0 d008 gpintgpen gpio interrupt and gpio enable register 0x01c2 000c 0x01c2 100c 0x01f0 c00c 0x01f0 d00c gpdatgpdir gpio data and gpio direction register 0x01c2 0010 0x01c2 1010 0x01f0 c010 0x01f0 d010 tim12 timer counter register 12 0x01c2 0014 0x01c2 1014 0x01f0 c014 0x01f0 d014 tim34 timer counter register 34 0x01c2 0018 0x01c2 1018 0x01f0 c018 0x01f0 d018 prd12 timer period register 12 0x01c2 001c 0x01c2 101c 0x01f0 c01c 0x01f0 d01c prd34 timer period register 34 0x01c2 0020 0x01c2 1020 0x01f0 c020 0x01f0 d020 tcr timer control register 0x01c2 0024 0x01c2 1024 0x01f0 c024 0x01f0 d024 tgcr timer global control register 0x01c2 0028 0x01c2 1028 0x01f0 c028 0x01f0 d028 wdtcr watchdog timer control register 0x01c2 0034 0x01c2 1034 0x01f0 c034 0x01f0 d034 rel12 timer reload register 12 0x01c2 0038 0x01c2 1038 0x01f0 c038 0x01f0 d038 rel34 timer reload register 34 0x01c2 003c 0x01c2 103c 0x01f0 c03c 0x01f0 d03c cap12 timer capture register 12 0x01c2 0040 0x01c2 1040 0x01f0 c040 0x01f0 d040 cap34 timer capture register 34 0x01c2 0044 0x01c2 1044 0x01f0 c044 0x01f0 d044 intctlstat timer interrupt control and status register 0x01c2 0060 0x01c2 1060 0x01f0 c060 0x01f0 d060 cmp0 compare register 0 0x01c2 0064 0x01c2 1064 0x01f0 c064 0x01f0 d064 cmp1 compare register 1 0x01c2 0068 0x01c2 1068 0x01f0 c068 0x01f0 d068 cmp2 compare register 2 0x01c2 006c 0x01c2 106c 0x01f0 c06c 0x01f0 d06c cmp3 compare register 3 0x01c2 0070 0x01c2 1070 0x01f0 c070 0x01f0 d070 cmp4 compare register 4 0x01c2 0074 0x01c2 1074 0x01f0 c074 0x01f0 d074 cmp5 compare register 5 0x01c2 0078 0x01c2 1078 0x01f0 c078 0x01f0 d078 cmp6 compare register 6 0x01c2 007c 0x01c2 107c 0x01f0 c07c 0x01f0 d07c cmp7 compare register 7 copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 157 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.21.1 timer electrical data/timing table 6-88. timing requirements for timer input (1) (2) (see figure 6-49 ) 1.2v, 1.1v, 1.0v no. unit min max 1 t c(tm64px_in12) cycle time, tm64px_in12 4p ns 2 t w(tinph) pulse duration, tm64px_in12 high 0.45c 0.55c ns 3 t w(tinpl) pulse duration, tm64px_in12 low 0.45c 0.55c ns 4 t t(tm64px_in12) transition time, tm64px_in12 0.05c or 10 (3) ns (1) p = oscin cycle time in ns. (2) c = tm64p0_in12 cycle time in ns. for example, when tm64px_in12 frequency is 27 mhz, use c = 37.0 37 ns (3) whichever is smaller. p = the period of the applied signal. maintaining transition times as fast as possible is recommended to improve noise immunity on input signals. figure 6-49. timer timing table 6-89. switching characteristics over recommended operating conditions for timer output (1) 1.2v, 1.1v, 1.0v no. parameter unit min max 5 t w(touth) pulse duration, tm64p0_out12 high 4p ns 6 t w(toutl) pulse duration, tm64p0_out12 low 4p ns (1) p = oscin cycle time in ns. figure 6-50. timer timing 158 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 tm64p0_out12 5 6 1 2 4 4 3 tm64p0_in12
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.22 real time clock (rtc) the rtc provides a time reference to an application running on the device. the current date and time is tracked in a set of counter registers that update once per second. the time can be represented in 12-hour or 24-hour mode. the calendar and time registers are buffered during reads and writes so that updates do not interfere with the accuracy of the time and date. alarms are available to interrupt the cpu at a particular time, or at periodic time intervals, such as once per minute or once per day. in addition, the rtc can interrupt the cpu every time the calendar and time registers are updated, or at programmable periodic intervals. the real-time clock (rtc) provides the following features: ? 100-year calendar (xx00 to xx99) ? counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation ? binary-coded-decimal (bcd) representation of time, calendar, and alarm ? 12-hour clock mode (with am and pm) or 24-hour clock mode ? alarm interrupt ? periodic interrupt ? single interrupt to the cpu ? supports external 32.768-khz crystal or external clock source of the same frequency ? separate isolated power supply figure 6-51 shows a block diagram of the rtc. figure 6-51. real-time clock block diagram copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 159 submit documentation feedback product folder links: am1802 seconds minutes hours days months years alarm timer alarminterrupts periodicinterrupts counter 32 khz oscillator compensation week days oscillator rtc_xi xtal rtc_xo
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.22.1 clock source the clock reference for the rtc is an external 32.768-khz crystal or an external clock source of the same frequency. the rtc also has a separate power supply that is isolated from the rest of the system. when the cpu and other peripherals are without power, the rtc can remain powered to preserve the current time and calendar information. even if the rtc is not used, it must remain powered when the rest of the device is powered. the source for the rtc reference clock may be provided by a crystal or by an external clock source. the rtc has an internal oscillator buffer to support direct operation with a crystal. the crystal is connected between pins rtc_xi and rtc_xo. rtc_xi is the input to the on-chip oscillator and rtc_xo is the output from the oscillator back to the crystal. an external 32.768-khz clock source may be used instead of a crystal. in such a case, the clock source is connected to rtc_xi, and rtc_xo is left unconnected. if the rtc is not used, the rtc_xi pin should be held either low or high, rtc_xo should be left unconnected, rtc_cvdd should be connected to the device cvdd and rtc_vss should remain grounded. figure 6-52. clock source 160 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 xtal 32.768 khz c2c1 rtc_xi rtc_xo rtc_v ss 32k osc real time clock (rtc) module isolated rtc power domain cv dd rtc_cv dd rtc power source
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.22.2 real-time clock register descriptions table 6-90. real-time clock (rtc) registers byte address acronym register description 0x01c2 3000 second seconds register 0x01c2 3004 minute minutes register 0x01c2 3008 hour hours register 0x01c2 300c day day of the month register 0x01c2 3010 month month register 0x01c2 3014 year year register 0x01c2 3018 dotw day of the week register 0x01c2 3020 alarmsecond alarm seconds register 0x01c2 3024 alarmminute alarm minutes register 0x01c2 3028 alarmhour alarm hours register 0x01c2 302c alarmday alarm days register 0x01c2 3030 alarmmonth alarm months register 0x01c2 3034 alarmyear alarm years register 0x01c2 3040 ctrl control register 0x01c2 3044 status status register 0x01c2 3048 interrupt interrupt enable register 0x01c2 304c complsb compensation (lsb) register 0x01c2 3050 compmsb compensation (msb) register 0x01c2 3054 osc oscillator register 0x01c2 3060 scratch0 scratch 0 (general-purpose) register 0x01c2 3064 scratch1 scratch 1 (general-purpose) register 0x01c2 3068 scratch2 scratch 2 (general-purpose) register 0x01c2 306c kick0 kick 0 (write protect) register 0x01c2 3070 kick1 kick 1 (write protect) register copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 161 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.23 general-purpose input/output (gpio) the gpio peripheral provides general-purpose pins that can be configured as either inputs or outputs. when configured as an output, a write to an internal register can control the state driven on the output pin. when configured as an input, the state of the input is detectable by reading the state of an internal register. in addition, the gpio peripheral can produce cpu interrupts and edma events in different interrupt/event generation modes. the gpio peripheral provides generic connections to external devices. the gpio pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of gpio [0:15]). the device gpio peripheral supports the following: ? up to 144 pins configurable as gpio ? external interrupt and dma request capability ? every gpio pin may be configured to generate an interrupt request on detection of rising and/or falling edges on the pin. ? the interrupt requests within each bank are combined (logical or) to create eight unique bank level interrupt requests. ? the bank level interrupt service routine may poll the intstatx register for its bank to determine which pin(s) have triggered the interrupt. ? gpio banks 0, 1, 2, 3, 4, 5, 6, 7 and 8 interrupts assigned to arm intc interrupt requests 42, 43, 44, 45, 46, 47, 48, 49 and 50 respectively ? gpio banks 0, 1, 2, 3, 4, and 5 are assigned to edma events 6, 7, 22, 23, 28, 29, and 29 respectively on channel controller 0 and gpio banks 6, 7, and 8 are assigned to edma events 16, 17, and 18 respectively on channel controller 1. ? set/clear functionality: firmware writes 1 to corresponding bit position(s) to set or to clear gpio signal(s). this allows multiple firmware processes to toggle gpio output signals without critical section protection (disable interrupts, program gpio, re-enable interrupts, to prevent context switching to anther process during gpio programming). ? separate input/output registers ? output register in addition to set/clear so that, if preferred by firmware, some gpio output signals can be toggled by direct write to the output register(s). ? output register, when read, reflects output drive status. this, in addition to the input register reflecting pin status and open-drain i/o cell, allows wired logic be implemented. the memory map for the gpio registers is shown in table 6-91 . 162 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.23.1 gpio register description(s) table 6-91. gpio registers byte address acronym register description 0x01e2 6000 rev peripheral revision register 0x01e2 6004 reserved reserved 0x01e2 6008 binten gpio interrupt per-bank enable register gpio banks 0 and 1 0x01e2 6010 dir01 gpio banks 0 and 1 direction register 0x01e2 6014 out_data01 gpio banks 0 and 1 output data register 0x01e2 6018 set_data01 gpio banks 0 and 1 set data register 0x01e2 601c clr_data01 gpio banks 0 and 1 clear data register 0x01e2 6020 in_data01 gpio banks 0 and 1 input data register 0x01e2 6024 set_ris_trig01 gpio banks 0 and 1 set rising edge interrupt register 0x01e2 6028 clr_ris_trig01 gpio banks 0 and 1 clear rising edge interrupt register 0x01e2 602c set_fal_trig01 gpio banks 0 and 1 set falling edge interrupt register 0x01e2 6030 clr_fal_trig01 gpio banks 0 and 1 clear falling edge interrupt register 0x01e2 6034 intstat01 gpio banks 0 and 1 interrupt status register gpio banks 2 and 3 0x01e2 6038 dir23 gpio banks 2 and 3 direction register 0x01e2 603c out_data23 gpio banks 2 and 3 output data register 0x01e2 6040 set_data23 gpio banks 2 and 3 set data register 0x01e2 6044 clr_data23 gpio banks 2 and 3 clear data register 0x01e2 6048 in_data23 gpio banks 2 and 3 input data register 0x01e2 604c set_ris_trig23 gpio banks 2 and 3 set rising edge interrupt register 0x01e2 6050 clr_ris_trig23 gpio banks 2 and 3 clear rising edge interrupt register 0x01e2 6054 set_fal_trig23 gpio banks 2 and 3 set falling edge interrupt register 0x01e2 6058 clr_fal_trig23 gpio banks 2 and 3 clear falling edge interrupt register 0x01e2 605c intstat23 gpio banks 2 and 3 interrupt status register gpio banks 4 and 5 0x01e2 6060 dir45 gpio banks 4 and 5 direction register 0x01e2 6064 out_data45 gpio banks 4 and 5 output data register 0x01e2 6068 set_data45 gpio banks 4 and 5 set data register 0x01e2 606c clr_data45 gpio banks 4 and 5 clear data register 0x01e2 6070 in_data45 gpio banks 4 and 5 input data register 0x01e2 6074 set_ris_trig45 gpio banks 4 and 5 set rising edge interrupt register 0x01e2 6078 clr_ris_trig45 gpio banks 4 and 5 clear rising edge interrupt register 0x01e2 607c set_fal_trig45 gpio banks 4 and 5 set falling edge interrupt register 0x01e2 6080 clr_fal_trig45 gpio banks 4 and 5 clear falling edge interrupt register 0x01e2 6084 intstat45 gpio banks 4 and 5 interrupt status register copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 163 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com table 6-91. gpio registers (continued) byte address acronym register description gpio banks 6 and 7 0x01e2 6088 dir67 gpio banks 6 and 7 direction register 0x01e2 608c out_data67 gpio banks 6 and 7 output data register 0x01e2 6090 set_data67 gpio banks 6 and 7 set data register 0x01e2 6094 clr_data67 gpio banks 6 and 7 clear data register 0x01e2 6098 in_data67 gpio banks 6 and 7 input data register 0x01e2 609c set_ris_trig67 gpio banks 6 and 7 set rising edge interrupt register 0x01e2 60a0 clr_ris_trig67 gpio banks 6 and 7 clear rising edge interrupt register 0x01e2 60a4 set_fal_trig67 gpio banks 6 and 7 set falling edge interrupt register 0x01e2 60a8 clr_fal_trig67 gpio banks 6 and 7 clear falling edge interrupt register 0x01e2 60ac intstat67 gpio banks 6 and 7 interrupt status register gpio bank 8 0x01e2 60b0 dir8 gpio bank 8 direction register 0x01e2 60b4 out_data8 gpio bank 8 output data register 0x01e2 60b8 set_data8 gpio bank 8 set data register 0x01e2 60bc clr_data8 gpio bank 8 clear data register 0x01e2 60c0 in_data8 gpio bank 8 input data register 0x01e2 60c4 set_ris_trig8 gpio bank 8 set rising edge interrupt register 0x01e2 60c8 clr_ris_trig8 gpio bank 8 clear rising edge interrupt register 0x01e2 60cc set_fal_trig8 gpio bank 8 set falling edge interrupt register 0x01e2 60d0 clr_fal_trig8 gpio bank 8 clear falling edge interrupt register 0x01e2 60d4 intstat8 gpio bank 8 interrupt status register 164 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 6.23.2 gpio peripheral input/output electrical data/timing table 6-92. timing requirements for gpio inputs (1) (see figure 6-53 ) 1.2v, 1.1v, 1.0v no. unit min max 1 t w(gpih) pulse duration, gp n [ m ] as input high 2c (1) (2) ns 2 t w(gpil) pulse duration, gp n [ m ] as input low 2c (1) (2) ns (1) the pulse width given is sufficient to generate a cpu interrupt or an edma event. however, if a user wants to have the device recognize the gpix changes through software polling of the gpio register, the gpix duration must be extended to allow the device enough time to access the gpio register through the internal bus. (2) c=sysclk4 period in ns. table 6-93. switching characteristics over recommended operating conditions for gpio outputs (see figure 6-53 ) 1.2v, 1.1v, 1.0v no. parameter unit min max 3 t w(gpoh) pulse duration, gp n [ m ] as output high 2c (1) (2) ns 4 t w(gpol) pulse duration, gp n [ m ] as output low 2c (1) (2) ns (1) this parameter value should not be used as a maximum performance specification. actual performance of back-to-back accesses of the gpio is dependent upon internal bus activity. (2) c=sysclk4 period in ns. figure 6-53. gpio port timing 6.23.3 gpio peripheral external interrupts electrical data/timing table 6-94. timing requirements for external interrupts (1) (see figure 6-54 ) 1.2v, 1.1v, 1.0v no. unit min max 1 t w(ilow) width of the external interrupt pulse low 2c (1) (2) ns 2 t w(ihigh) width of the external interrupt pulse high 2c (1) (2) ns (1) the pulse width given is sufficient to generate an interrupt or an edma event. however, if a user wants to have the device recognize the gpio changes through software polling of the gpio register, the gpio duration must be extended to allow the device enough time to access the gpio register through the internal bus. (2) c=sysclk4 period in ns. figure 6-54. gpio external interrupt timing copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 165 submit documentation feedback product folder links: am1802 gp [ ] as input n m 2 1 gp [ ] as input n m gp n m [ ] as output 4 3 2 1
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.24 emulation logic this section describes the steps to use a third party debugger on the arm926ej-s within the device. the debug capabilities and features for arm are as shown below. arm: ? basic debug ? execution control ? system visibility ? advanced debug ? global start ? global stop ? advanced system control ? subsystem reset via debug ? peripheral notification of debug events ? cache-coherent debug accesses ? program trace ? program flow corruption ? code coverage ? path coverage ? thread/interrupt synchronization problems ? data trace ? memory corruption ? timing trace ? profiling ? analysis actions ? stop program execution ? control trace streams ? generate debug interrupt ? benchmarking with counters ? external trigger generation ? debug state machine state transition ? combinational and sequential event generation ? analysis events ? program event detection ? data event detection ? external trigger detection ? system event detection (i.e. cache miss) ? debug state machine state detection ? analysis configuration ? application access ? debugger access 166 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-95. arm debug features category hardware feature availability software breakpoint unlimited up to 14 hwbps, including: 2 precise (1) hwbp inside arm core which are shared with watch points. basic debug hardware breakpoint 8 imprecise (1) hwbps from etm ? s address comparators, which are shared with trace function, and can be used as watch points. 4 imprecise (1) hwbps from icecrusher. up to 6 watch points, including: 2 from arm core which is shared with hwbps and can be associated with a data. watch point 8 from etm ? s address comparators, which are shared with trace function, and hwbps. 2 from arm core which is shared with hwbps. analysis watch point with data 8 watch points from etm can be associated with a data comparator, and etm has total 4 data comparators. counters/timers 3x32-bit (1 cycle ; 2 event) external event trigger in 1 external event trigger out 1 address range for trace 4 data qualification for trace 2 system events for trace control 20 trace control counters/timers for trace control 2x16-bit state machines/sequencers 1x3-state state machine context/thread id comparator 1 independent trigger control units 12 capture depth pc 4k bytes etb on-chip trace capture depth pc + timing 4k bytes etb capture application accessible y (1) precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. imprecise breakpoints will halt the processor some number of cycles after the selected instruction depending on device conditions. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 167 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.24.1 jtag port description the device target debug interface uses the five standard ieee 1149.1(jtag) signals ( trst, tck, tms, tdi, and tdo), a return clock (rtck) due to the clocking requirements of the arm926ej-s and emulation signals emu0 and emu1. trst holds the debug and boundary scan logic in reset when pulled low (its default state). since trst has an internal pull-down resistor, this ensures that at power up the device functions in its normal (non-test) operation mode if trst is not connected. otherwise, trst should be driven inactive by the emulator or boundary scan controller. boundary scan test cannot be performed while the trst pin is pulled low. table 6-96. jtag port description pin type name description when asserted (active low) causes all test and debug logic in the device to be reset trst i test logic reset along with the ieee 1149.1 interface this is the test clock used to drive an ieee 1149.1 tap state machine and logic. tck i test clock depending on the emulator attached to , this is a free running clock or a gated clock depending on rtck monitoring. synchronized tck. depending on the emulator attached to, the jtag signals are rtck o returned test clock clocked from rtck or rtck is monitored by the emulator to gate tck. tms i test mode select directs the next state of the ieee 1149.1 test access port state machine tdi i test data input scan data input to the device tdo o test data output scan data output of the device emu0 i/o emulation 0 channel 0 trigger + hsrtdx emu1 i/o emulation 1 channel 1 trigger + hsrtdx 6.24.2 scan chain configuration parameters table 6-97 shows the tap configuration details required to configure the router/emulator for this device. table 6-97. jtag port description router port id default tap tap name tap ir length 17 no reserved 38 18 no arm926 4 19 no etb 4 the router is revision c and has a 6-bit ir length. 6.24.3 initial scan chain configuration the first level of debug interface that sees the scan controller is the tap router module. the debugger can configure the tap router for serially linking up to 16 tap controllers or individually scanning one of the tap controllers without disrupting the ir state of the other taps. 6.24.3.1 adding taps to the scan chain the tap router must be programmed to add additional taps to the scan chain. the following jtag scans must be completed to add the arm926ej-s to the scan chain. a power-on reset (por) or the jtag test-logic reset state configures the tap router to contain only the router ? s tap. 168 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 figure 6-55. adding arm926ej-s to the scan chain pre-amble : the device whose data reaches the emulator first is listed first in the board configuration file. this device is a pre-amble for all the other devices. this device has the lowest device id. post-amble : the device whose data reaches the emulator last is listed last in the board configuration file. this device is a post-amble for all the other devices. this device has the highest device id. ? function : update the jtag preamble and post-amble counts. ? parameter : the ir pre-amble count is '0'. ? parameter : the ir post-amble count is '0'. ? parameter : the dr pre-amble count is '0'. ? parameter : the dr post-amble count is '0'. ? parameter : the ir main count is '6'. ? parameter : the dr main count is '1'. ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-ir'. ? parameter : the jtag destination state is 'pause-ir'. ? parameter : the bit length of the command is '6'. ? parameter : the send data value is '0x00000007'. ? parameter : the actual receive data is 'discarded'. ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-dr'. ? parameter : the jtag destination state is 'pause-dr'. ? parameter : the bit length of the command is '8'. ? parameter : the send data value is '0x00000089'. ? parameter : the actual receive data is 'discarded'. ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-ir'. ? parameter : the jtag destination state is 'pause-ir'. ? parameter : the bit length of the command is '6'. ? parameter : the send data value is '0x00000002'. ? parameter : the actual receive data is 'discarded'. ? function : embed the port address in next command. ? parameter : the port address field is '0x0f000000'. ? parameter : the port address value is '3'. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 169 submit documentation feedback product folder links: am1802 tdo router tdi steps clk tms router arm926ej-s/etm
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-dr'. ? parameter : the jtag destination state is 'pause-dr'. ? parameter : the bit length of the command is '32'. ? parameter : the send data value is '0xa2002108'. ? parameter : the actual receive data is 'discarded'. ? function : do a send-only all-ones jtag ir/dr scan. ? parameter : the jtag shift state is 'shift-ir'. ? parameter : the jtag destination state is 'run-test/idle'. ? parameter : the bit length of the command is '6'. ? parameter : the send data value is 'all-ones'. ? parameter : the actual receive data is 'discarded'. ? function : wait for a minimum number of tclk pulses. ? parameter : the count of tclk pulses is '10'. ? function : update the jtag preamble and post-amble counts. ? parameter : the ir pre-amble count is '0'. ? parameter : the ir post-amble count is '6'. ? parameter : the dr pre-amble count is '0'. ? parameter : the dr post-amble count is '1'. ? parameter : the ir main count is '4'. ? parameter : the dr main count is '1'. the initial scan chain contains only the tap router module. the following steps must be completed in order to add etb tap to the scan chain. figure 6-56. adding etb to the scan chain ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-ir'. ? parameter : the jtag destination state is 'pause-ir'. ? parameter : the bit length of the command is '6'. ? parameter : the send data value is '0x00000007'. ? parameter : the actual receive data is 'discarded'. 170 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802 tdi router arm926ej-s/etm tdo steps clk tms router arm926ej-s/etm etb
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-dr'. ? parameter : the jtag destination state is 'pause-dr'. ? parameter : the bit length of the command is '8'. ? parameter : the send data value is '0x00000089'. ? parameter : the actual receive data is 'discarded'. ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-ir'. ? parameter : the jtag destination state is 'pause-ir'. ? parameter : the bit length of the command is '6'. ? parameter : the send data value is '0x00000002'. ? parameter : the actual receive data is 'discarded'. ? function : embed the port address in next command. ? parameter : the port address field is '0x0f000000'. ? parameter : the port address value is '3'. ? function : do a send-only jtag ir/dr scan. ? parameter : the route to jtag shift state is 'shortest transition'. ? parameter : the jtag shift state is 'shift-dr'. ? parameter : the jtag destination state is 'pause-dr'. ? parameter : the bit length of the command is '32'. ? parameter : the send data value is '0xa3302108'. ? parameter : the actual receive data is 'discarded'. ? function : do a send-only all-ones jtag ir/dr scan. ? parameter : the jtag shift state is 'shift-ir'. ? parameter : the jtag destination state is 'run-test/idle'. ? parameter : the bit length of the command is '6'. ? parameter : the send data value is 'all-ones'. ? parameter : the actual receive data is 'discarded'. ? function : wait for a minimum number of tclk pulses. ? parameter : the count of tclk pulses is '10'. ? function : update the jtag preamble and post-amble counts. ? parameter : the ir pre-amble count is '0'. ? parameter : the ir post-amble count is '6 + 4'. ? parameter : the dr pre-amble count is '0'. ? parameter : the dr post-amble count is '1 + 1'. ? parameter : the ir main count is '4'. ? parameter : the dr main count is '1'. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 171 submit documentation feedback product folder links: am1802
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 6.24.4 ieee 1149.1 jtag the jtag (1) interface is used for bsdl testing and emulation of the device. the device requires that both trst and reset be asserted upon power up to be properly initialized. while reset initializes the device, trst initializes the device's emulation logic. both resets are required for proper operation. while both trst and reset need to be asserted upon power up, only reset needs to be released for the device to boot properly. trst may be asserted indefinitely for normal operation, keeping the jtag port interface and device's emulation logic in the reset state. trst only needs to be released when it is necessary to use a jtag controller to debug the device or exercise the device's boundary scan functionality. note: trst is synchronous and must be clocked by tck; otherwise, the boundary scan logic may not respond as expected after trst is asserted. reset must be released only in order for boundary-scan jtag to read the variant field of idcode correctly. other boundary-scan instructions work correctly independent of current state of reset. for maximum reliability, the device includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. jtag controllers from texas instruments actively drive trst high. however, some third-party jtag controllers may not drive trst high but expect the use of a pullup resistor on trst. when using this type of jtag controller, assert trst to initialize the device after powerup and externally drive trst high before attempting any emulation or boundary scan operations. 6.24.4.1 jtag peripheral register description(s) - jtag id register (devidr0) table 6-98. devidr0 register byte address acronym register description comments read-only. provides 32-bit 0x01c1 4018 devidr0 jtag identification register jtag id of the device. (1) ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. the jtag id register is a read-only register that identifies to the customer the jtag/device id. for the device, the jtag id register resides at address location 0x01c1 4018. the register hex value for each silicon revision is ? 0x1b7d 102f for silicon revision 2.0 for the actual register bit names and their associated bit field descriptions, see figure 6-57 and table 6- 99 . figure 6-57. jtag id (devidr0) register description - register value 31-28 27-12 11-1 0 variant (4-bit) part number (16-bit) manufacturer (11-bit) lsb r-xxxx r-1011 0111 1101 0001 r-0000 0010 111 r-1 legend: r = read, w = write, n = value at reset 172 peripheral information and electrical specifications copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 table 6-99. jtag id register selection bit descriptions bit name description 31:28 variant variant (4-bit) value 27:12 part number part number (16-bit) value 11-1 manufacturer manufacturer (11-bit) value 0 lsb lsb. this bit is read as a "1". 6.24.4.2 jtag test-port electrical data/timing table 6-100. timing requirements for jtag test port (see figure 6-58 ) 1.2v 1.1v 1.0v no. unit min max min max min max 1 t c(tck) cycle time, tck 40 50 66.6 ns 2 t w(tckh) pulse duration, tck high 16 20 26.6 ns 3 t w(tckl) pulse duration, tck low 16 20 26.6 ns 4 t c(rtck) cycle time, rtck 40 50 66.6 ns 5 t w(rtckh) pulse duration, rtck high 16 20 26.6 ns 6 t w(rtckl) pulse duration, rtck low 16 20 26.6 ns 7 t su(tdiv-rtckh) setup time, tdi/tms/ trst valid before rtck high 4 4 4 ns 8 t h(rtckh-tdiv) hold time, tdi/tms/ trst valid after rtck high 4 6 8 ns table 6-101. switching characteristics over recommended operating conditions for jtag test port (see figure 6-58 ) 1.2v 1.1v 1.0v no. parameter unit min max min max min max 9 t d(rtckl-tdov) delay time, rtck low to tdo valid 18 23 31 ns figure 6-58. jtag test-port timing 6.24.5 jtag 1149.1 boundary scan considerations to use boundary scan, the following sequence should be followed: ? execute a valid reset sequence and exit reset ? wait at least 6000 oscin clock cycles ? enter boundary scan mode using the jtag pins no specific value is required on the emu0 and emu1 pins for boundary scan testing. if trst is not driven by the boundary scan tool or tester, trst should be externally pulled high during boundary scan testing. copyright ? 2010 ? 2014, texas instruments incorporated peripheral information and electrical specifications 173 submit documentation feedback product folder links: am1802 tck tdo 1 7 2 3 rtck 4 5 6 9 8 tdi/tms/trst
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 7 device and documentation support 7.1 device support 7.1.1 development support ti offers an extensive line of development tools for the device platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the tool's support documentation is electronically available within the code composer studio ? integrated development environment (ide). the following products support development of the device applications: software development tools: code composer studio ? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools hardware development tools: extended development system (xds ? ) emulator for a complete listing of development-support tools for the device, visit the texas instruments web site on the worldwide web at www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. 7.1.2 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all am1xxx processors and support tools. each commercial am1xxx platform member has one of three prefixes: x, p, or null (no prefix). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmdx) through fully qualified production devices/tools (tmds). device development evolutionary flow: x experimental device that is not necessarily representative of the final device's electrical specifications. p final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. null fully-qualified production device. support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product. x and p devices and tmdx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." null devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (x or p) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. figure 7-1 provides a legend for reading the complete device. 174 device and documentation support copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 a. bga = ball grid array b. parts marked revision b are silicon revision 2.1 if ' 21 ' is marked on the package and silicon revision 2.0 if there is no ' 21 ' marking. figure 7-1. device nomenclature 7.2 documentation support the following documents describe the device. copies of these documents are available on the internet at www.ti.com . tip: enter the literature number in the search box provided at www.ti.com. reference guides sprugx5 am1802 arm microprocessor system reference guide. describes the am1802 arm microprocessor (mpu) system. sprufu0 am17x/am18x arm microprocessor peripherals overview reference guide. provides an overview and briefly describes the peripherals available on the am17x/am18x arm microprocessors. 7.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki. established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 7.4 trademarks e2e is a trademark of texas instruments. arm926ej-s, ice-rt, arm9 are trademarks of arm ltd. arm, thumb, jazelle are registered trademarks of arm ltd. windows is a registered trademark of microsoft. i 2 c bus is a trademark of phillips. all other trademarks are the property of their respective owners. copyright ? 2010 ? 2014, texas instruments incorporated device and documentation support 175 submit documentation feedback product folder links: am1802 ( ) am1802 ( ) zwt ( ) 3 prefix x = experimental device devicesilicon revision 3 = 300 mhz package type device speed range temperature range (junction) b = silicon revision 2.0 or 2.1e = silicon revision 2.3 d = -40c to 90c (industrial grade) 361-pin plastic bga, with pb-freesoldered balls [green]; 0.65-mm ball pitch zce = (b) (a) p = prototype device blank = production device 361-pin plastic bga, with pb-freesoldered balls [green]; 0.80-mm ball pitch zwt =
am1802 sprs710e ? november 2010 ? revised march 2014 www.ti.com 7.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 7.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms and definitions. 8 mechanical packaging and orderable information this section describes the packaging options, materials, thermal and mechanical parameters. 8.1 thermal data for zce package the following table shows the thermal resistance characteristics for the pbga-zce mechanical package. table 8-1. thermal resistance characteristics (pbga package) [zce] no. c/w (1) air flow (m/s) (2) 1 r jc junction-to-case 7.6 n/a 2 r jb junction-to-board 11.3 n/a 3 r ja junction-to-free air 23.9 0.00 4 21.2 0.50 5 20.3 1.00 r jma junction-to-moving air 6 19.5 2.00 7 18.6 4.00 8 0.2 0.00 9 0.3 0.50 10 psi jt junction-to-package top 0.3 1.00 11 0.4 2.00 12 0.5 4.00 13 11.2 0.00 14 11.1 0.50 15 psi jb junction-to-board 11.1 1.00 16 11.0 2.00 17 10.9 4.00 (1) these measurements were conducted in a jedec defined 2s2p system and will change based on environment as well as application. for more information, see these eia/jedec standards - eia/jesd51-2, integrated circuits thermal test method environment conditions - natural convection (still air) and jesd51-7, high effective thermal conductivity test board for leaded surface mount packages . power dissipation of 500 mw and ambient temp of 70c assumed. pcb with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness (2) m/s = meters per second 176 mechanical packaging and orderable information copyright ? 2010 ? 2014, texas instruments incorporated submit documentation feedback product folder links: am1802
am1802 www.ti.com sprs710e ? november 2010 ? revised march 2014 8.2 thermal data for zwt package the following table shows the thermal resistance characteristics for the pbga-zwt mechanical package. table 8-2. thermal resistance characteristics (pbga package) [zwt] no. c/w (1) air flow (m/s) (2) 1 r jc junction-to-case 7.3 n/a 2 r jb junction-to-board 12.4 n /a 3 r ja junction-to-free air 23.7 0.00 4 21.0 0.50 5 20.1 1.00 r jma junction-to-moving air 6 19.3 2.00 7 18.4 4.00 8 0.2 0.00 9 0.3 0.50 10 psi jt junction-to-package top 0.3 1.00 11 0.4 2.00 12 0.5 4.00 13 12.3 0.00 14 12.2 0.50 15 psi jb junction-to-board 12.1 1.00 16 12.0 2.00 17 11.9 4.00 (1) these measurements were conducted in a jedec defined 2s2p system and will change based on environment as well as application. for more information, see these eia/jedec standards - eia/jesd51-2, integrated circuits thermal test method environment conditions - natural convection (still air) and jesd51-7, high effective thermal conductivity test board for leaded surface mount packages . power dissipation of 1w and ambient temp of 70c assumed. pcb with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness (2) m/s = meters per second 8.3 packaging information the following packaging information and addendum reflect the most current data available for the designated device(s). this data is subject to change without notice and without revision of this document. copyright ? 2010 ? 2014, texas instruments incorporated mechanical packaging and orderable information 177 submit documentation feedback product folder links: am1802
package option addendum www.ti.com 19-may-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples am1802bzced3 nrnd nfbga zce 361 160 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 am1802b zce d300 am1802bzwtd3 nrnd nfbga zwt 361 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 am1802b zwt d300 am1802ezced3 active nfbga zce 361 160 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 am1802e zce d300 am1802ezwtd3 active nfbga zwt 361 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 90 am1802e zwt d300 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 19-may-2015 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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